Full Adder Circuit. Part I

Grzegorz Bancerek

Institute of Mathematics, Polish Academy of Sciences

Yatsuka Nakamura

Shinshu University, Nagano

Summary.

We continue the formalisation of circuits started by Piotr Rudnicki, Andrzej Trybulec, Pauline Kawamoto, and the second author in [12], [13], [11], [14]. The first step in proving properties of full $n$-bit adder circuit, i.e. 1-bit adder, is presented. We employ the notation of combining circuits introduced in [10].

This work was written while the first author visited Shinshu University, July--August 1994.

MML Identifier: FACIRC_1

Contents (PDF format)

1. Combining of Many Sorted Signatures
2. Combining of Circuits
3. Signatures with One Operation
4. Unsplit Condition
5. One Gate Circuits
6. Boolean Circuits
7. One Bit Adder

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