Full Subtracter Circuit. Part II

Shin'nosuke Yamaguchi

Shinshu University, Nagano

Grzegorz Bancerek

Bialystok Technical University

Katsumi Wasaki

Shinshu University, Nagano

Summary.

In this article we continue investigations from [22] of verification of a design of subtracter circuit. We define it as a combination of multi cell circuit using schemes from [6]. As the main result we prove the stability of the circuit.

MML Identifier: FSCIRC_2

Contents (PDF format)

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