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From: yodaiken@sphinx.nmt.edu (Victor Yodaiken)
Date: Wed, 23 Nov 1994 09:42:50 -0700
In-Reply-To: mel@ultrastar.EE.CORNELL.EDU (Miriam Leeser)
       "Mark Aagaard's work on verifying pipelines" (Nov 23, 10:05am)
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Subject: Re: Mark Aagaard's work on verifying pipelines
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On Nov 23, 10:05am, Miriam Leeser wrote:
>
>This approach is building infrastructure that will allow others to
>verify real pipelined circuits in the future. 
>

I'd just like to clarify my argument before I bow out of this discussion.
It is not my intent to disparage  the work done in hardware 
verification  -- in fact, I find this work to be  very interesting and
important.  But, I do think we should not confuse research that is  aimed
at "building infrastructure" with the capacity to   actually
verify significant circuits. It may well be the case that 
this research  "will allow others" to perform such verifications
"in the future". We shall see. 

While we are at it, does anyone have some  concrete information about the
types of errors that are likely to be found in circuit designs. My
unsubstantiated guess is that timing errors are far more common than
logic errors and that the growing popularity of such circuit disciplines
as asynchronous circuits and wave pipelining will only increase that share.
Do others have contrary  guesses or even some hard data?