thus
not ].r,s.[ is left_end
not ].r,s.[ is right_end
assume
].r,s.[ is right_end
; contradiction
then A7:
sup ].r,s.[ in ].r,s.[
;
then A8:
sup ].r,s.[ < s
by XXREAL_1:4;
r < sup ].r,s.[
by A7, XXREAL_1:4;
then
r < s
by A8, XXREAL_0:2;
then
s = sup ].r,s.[
by Th32;
hence
contradiction
by A7, XXREAL_1:4; verum