let x1, x2, x3, x4, x5, x6, x7 be non pair set ; :: thesis: for s being State of (STC0ICirc (x1,x2,x3,x4,x5,x6,x7))
for a123, a567 being Element of BOOLEAN st a123 = s . (GFA0AdderOutput (x1,x2,x3)) & a567 = s . (GFA0AdderOutput (x5,x6,x7)) holds
(Following s) . [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,xor2] = a123 'xor' a567
set S = STC0IStr (x1,x2,x3,x4,x5,x6,x7);
set C = STC0ICirc (x1,x2,x3,x4,x5,x6,x7);
set A1out = GFA0AdderOutput (x1,x2,x3);
set A2out = GFA0AdderOutput (x5,x6,x7);
set A1A20 = [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,xor2];
let s be State of (STC0ICirc (x1,x2,x3,x4,x5,x6,x7)); :: thesis: for a123, a567 being Element of BOOLEAN st a123 = s . (GFA0AdderOutput (x1,x2,x3)) & a567 = s . (GFA0AdderOutput (x5,x6,x7)) holds
(Following s) . [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,xor2] = a123 'xor' a567
let a123, a567 be Element of BOOLEAN ; :: thesis: ( a123 = s . (GFA0AdderOutput (x1,x2,x3)) & a567 = s . (GFA0AdderOutput (x5,x6,x7)) implies (Following s) . [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,xor2] = a123 'xor' a567 )
assume A1: ( a123 = s . (GFA0AdderOutput (x1,x2,x3)) & a567 = s . (GFA0AdderOutput (x5,x6,x7)) ) ; :: thesis: (Following s) . [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,xor2] = a123 'xor' a567
A2: dom s = the carrier of (STC0IStr (x1,x2,x3,x4,x5,x6,x7)) by CIRCUIT1:3;
A3: ( GFA0AdderOutput (x1,x2,x3) in the carrier of (STC0IStr (x1,x2,x3,x4,x5,x6,x7)) & GFA0AdderOutput (x5,x6,x7) in the carrier of (STC0IStr (x1,x2,x3,x4,x5,x6,x7)) ) by ThSTC0IS6;
InnerVertices (STC0IStr (x1,x2,x3,x4,x5,x6,x7)) = the carrier' of (STC0IStr (x1,x2,x3,x4,x5,x6,x7)) by FACIRC_1:37;
hence (Following s) . [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,xor2] = xor2 . (s * <*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>) by ThSTC0IS7, FACIRC_1:35
.= xor2 . <*a123,a567*> by A1, A3, A2, FINSEQ_2:125
.= a123 'xor' a567 by FACIRC_1:def 4 ;
:: thesis: verum