let x1, x2, x3, x5, x6, x7 be non pair set ; :: thesis: for x4 being set
for s being State of (STC0ICirc (x1,x2,x3,x4,x5,x6,x7))
for a123567, a567x4, ax4123 being Element of BOOLEAN st a123567 = s . [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,and2] & a567x4 = s . [<*(GFA0AdderOutput (x5,x6,x7)),x4*>,and2] & ax4123 = s . [<*x4,(GFA0AdderOutput (x1,x2,x3))*>,and2] holds
(Following s) . (GFA0CarryOutput ((GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7)),x4)) = (a123567 'or' a567x4) 'or' ax4123
let x4 be set ; :: thesis: for s being State of (STC0ICirc (x1,x2,x3,x4,x5,x6,x7))
for a123567, a567x4, ax4123 being Element of BOOLEAN st a123567 = s . [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,and2] & a567x4 = s . [<*(GFA0AdderOutput (x5,x6,x7)),x4*>,and2] & ax4123 = s . [<*x4,(GFA0AdderOutput (x1,x2,x3))*>,and2] holds
(Following s) . (GFA0CarryOutput ((GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7)),x4)) = (a123567 'or' a567x4) 'or' ax4123
set S = STC0IStr (x1,x2,x3,x4,x5,x6,x7);
set C = STC0ICirc (x1,x2,x3,x4,x5,x6,x7);
set A1out = GFA0AdderOutput (x1,x2,x3);
set A2out = GFA0AdderOutput (x5,x6,x7);
set A1A2 = [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,and2];
set A2x4 = [<*(GFA0AdderOutput (x5,x6,x7)),x4*>,and2];
set x4A1 = [<*x4,(GFA0AdderOutput (x1,x2,x3))*>,and2];
let s be State of (STC0ICirc (x1,x2,x3,x4,x5,x6,x7)); :: thesis: for a123567, a567x4, ax4123 being Element of BOOLEAN st a123567 = s . [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,and2] & a567x4 = s . [<*(GFA0AdderOutput (x5,x6,x7)),x4*>,and2] & ax4123 = s . [<*x4,(GFA0AdderOutput (x1,x2,x3))*>,and2] holds
(Following s) . (GFA0CarryOutput ((GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7)),x4)) = (a123567 'or' a567x4) 'or' ax4123
let a123567, a567x4, ax4123 be Element of BOOLEAN ; :: thesis: ( a123567 = s . [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,and2] & a567x4 = s . [<*(GFA0AdderOutput (x5,x6,x7)),x4*>,and2] & ax4123 = s . [<*x4,(GFA0AdderOutput (x1,x2,x3))*>,and2] implies (Following s) . (GFA0CarryOutput ((GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7)),x4)) = (a123567 'or' a567x4) 'or' ax4123 )
assume A1: ( a123567 = s . [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,and2] & a567x4 = s . [<*(GFA0AdderOutput (x5,x6,x7)),x4*>,and2] & ax4123 = s . [<*x4,(GFA0AdderOutput (x1,x2,x3))*>,and2] ) ; :: thesis: (Following s) . (GFA0CarryOutput ((GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7)),x4)) = (a123567 'or' a567x4) 'or' ax4123
A2: dom s = the carrier of (STC0IStr (x1,x2,x3,x4,x5,x6,x7)) by CIRCUIT1:3;
A3: ( [<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,and2] in the carrier of (STC0IStr (x1,x2,x3,x4,x5,x6,x7)) & [<*(GFA0AdderOutput (x5,x6,x7)),x4*>,and2] in the carrier of (STC0IStr (x1,x2,x3,x4,x5,x6,x7)) & [<*x4,(GFA0AdderOutput (x1,x2,x3))*>,and2] in the carrier of (STC0IStr (x1,x2,x3,x4,x5,x6,x7)) ) by ThSTC0IS6;
InnerVertices (STC0IStr (x1,x2,x3,x4,x5,x6,x7)) = the carrier' of (STC0IStr (x1,x2,x3,x4,x5,x6,x7)) by FACIRC_1:37;
hence (Following s) . (GFA0CarryOutput ((GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7)),x4)) = or3 . (s * <*[<*(GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7))*>,and2],[<*(GFA0AdderOutput (x5,x6,x7)),x4*>,and2],[<*x4,(GFA0AdderOutput (x1,x2,x3))*>,and2]*>) by ThSTC0IS7, FACIRC_1:35
.= or3 . <*a123567,a567x4,ax4123*> by A1, A3, A2, FINSEQ_2:126
.= (a123567 'or' a567x4) 'or' ax4123 by FACIRC_1:def 7 ;
:: thesis: verum