let x1, x2, x3, x4, x5, x6, x7 be non pair set ; :: thesis: for s being State of (STC0ICirc (x1,x2,x3,x4,x5,x6,x7))
for a1, a2, a3, a4, a5, a6, a7 being Element of BOOLEAN st a1 = s . x1 & a2 = s . x2 & a3 = s . x3 & a4 = s . x4 & a5 = s . x5 & a6 = s . x6 & a7 = s . x7 holds
(Following (s,2)) . (STC0ICarryOutputC1 (x1,x2,x3,x4,x5,x6,x7)) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1)
set C = STC0ICirc (x1,x2,x3,x4,x5,x6,x7);
set S1 = STC0IIStr (x1,x2,x3,x5,x6,x7);
set C1 = STC0IICirc (x1,x2,x3,x5,x6,x7);
set A1out = GFA0AdderOutput (x1,x2,x3);
set A2out = GFA0AdderOutput (x5,x6,x7);
set S2 = BitGFA0Str ((GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7)),x4);
set C2 = BitGFA0Circ ((GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7)),x4);
set C1out = STC0IICarryOutputC1 (x1,x2,x3,x5,x6,x7);
let s be State of (STC0ICirc (x1,x2,x3,x4,x5,x6,x7)); :: thesis: for a1, a2, a3, a4, a5, a6, a7 being Element of BOOLEAN st a1 = s . x1 & a2 = s . x2 & a3 = s . x3 & a4 = s . x4 & a5 = s . x5 & a6 = s . x6 & a7 = s . x7 holds
(Following (s,2)) . (STC0ICarryOutputC1 (x1,x2,x3,x4,x5,x6,x7)) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1)
let a1, a2, a3, a4, a5, a6, a7 be Element of BOOLEAN ; :: thesis: ( a1 = s . x1 & a2 = s . x2 & a3 = s . x3 & a4 = s . x4 & a5 = s . x5 & a6 = s . x6 & a7 = s . x7 implies (Following (s,2)) . (STC0ICarryOutputC1 (x1,x2,x3,x4,x5,x6,x7)) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) )
assume A2: ( a1 = s . x1 & a2 = s . x2 & a3 = s . x3 & a4 = s . x4 & a5 = s . x5 & a6 = s . x6 & a7 = s . x7 ) ; :: thesis: (Following (s,2)) . (STC0ICarryOutputC1 (x1,x2,x3,x4,x5,x6,x7)) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1)
reconsider t = s as State of ((STC0IICirc (x1,x2,x3,x5,x6,x7)) +* (BitGFA0Circ ((GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7)),x4))) ;
reconsider s1 = s | the carrier of (STC0IIStr (x1,x2,x3,x5,x6,x7)) as State of (STC0IICirc (x1,x2,x3,x5,x6,x7)) by FACIRC_1:26;
A3: dom s1 = the carrier of (STC0IIStr (x1,x2,x3,x5,x6,x7)) by CIRCUIT1:3;
( STC0IICarryOutputC1 (x1,x2,x3,x5,x6,x7) in the carrier of (STC0IIStr (x1,x2,x3,x5,x6,x7)) & InputVertices (STC0IIStr (x1,x2,x3,x5,x6,x7)) misses InnerVertices (BitGFA0Str ((GFA0AdderOutput (x1,x2,x3)),(GFA0AdderOutput (x5,x6,x7)),x4)) ) by LmSTC0IS2b;
then A4: (Following (t,2)) . (STC0IICarryOutputC1 (x1,x2,x3,x5,x6,x7)) = (Following (s1,2)) . (STC0IICarryOutputC1 (x1,x2,x3,x5,x6,x7)) by FACIRC_1:32;
( a1 = s1 . x1 & a2 = s1 . x2 & a3 = s1 . x3 & a5 = s1 . x5 & a6 = s1 . x6 & a7 = s1 . x7 ) by ThSTC0IIS6, A2, A3, FUNCT_1:47;
hence (Following (s,2)) . (STC0ICarryOutputC1 (x1,x2,x3,x4,x5,x6,x7)) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) by A4, ThSTC0IIS10; :: thesis: verum