set f1 = and2c ;
set f2 = and2a ;
set f3 = and2 ;
set f0 = xor2c ;
let x, y, z be set ; :: thesis: ( z <> [<*x,y*>,xor2c] & x <> [<*y,z*>,and2a] & y <> [<*z,x*>,and2] & z <> [<*x,y*>,and2c] implies InputVertices (BitGFA1Str (x,y,z)) = {x,y,z} )
assume A1: ( z <> [<*x,y*>,xor2c] & x <> [<*y,z*>,and2a] & y <> [<*z,x*>,and2] & z <> [<*x,y*>,and2c] ) ; :: thesis: InputVertices (BitGFA1Str (x,y,z)) = {x,y,z}
set S2 = GFA1CarryStr (x,y,z);
set S1 = GFA1AdderStr (x,y,z);
( InputVertices (GFA1AdderStr (x,y,z)) = {x,y,z} & InputVertices (GFA1CarryStr (x,y,z)) = {x,y,z} ) by A1, Th45, FACIRC_1:57;
hence InputVertices (BitGFA1Str (x,y,z)) = {x,y,z} by CIRCCOMB:47, FACIRC_2:21; :: thesis: verum