let am, bp, cm, dp be non pair set ; :: thesis: for cin being set
for s being State of (BitFTA2Circ (am,bp,cm,dp,cin))
for a123x, a123y, a123z being Element of BOOLEAN st a123x = s . [<*(GFA2AdderOutput (am,bp,cm)),cin*>,and2c] & a123y = s . [<*cin,dp*>,and2a] & a123z = s . [<*dp,(GFA2AdderOutput (am,bp,cm))*>,and2] holds
(Following s) . (GFA1CarryOutput ((GFA2AdderOutput (am,bp,cm)),cin,dp)) = (a123x 'or' a123y) 'or' a123z
let cin be set ; :: thesis: for s being State of (BitFTA2Circ (am,bp,cm,dp,cin))
for a123x, a123y, a123z being Element of BOOLEAN st a123x = s . [<*(GFA2AdderOutput (am,bp,cm)),cin*>,and2c] & a123y = s . [<*cin,dp*>,and2a] & a123z = s . [<*dp,(GFA2AdderOutput (am,bp,cm))*>,and2] holds
(Following s) . (GFA1CarryOutput ((GFA2AdderOutput (am,bp,cm)),cin,dp)) = (a123x 'or' a123y) 'or' a123z
set S = BitFTA2Str (am,bp,cm,dp,cin);
set C = BitFTA2Circ (am,bp,cm,dp,cin);
set A1 = GFA2AdderOutput (am,bp,cm);
set A2 = GFA1CarryOutput ((GFA2AdderOutput (am,bp,cm)),cin,dp);
set A1cin = [<*(GFA2AdderOutput (am,bp,cm)),cin*>,and2c];
set cindp = [<*cin,dp*>,and2a];
set dpA1 = [<*dp,(GFA2AdderOutput (am,bp,cm))*>,and2];
let s be State of (BitFTA2Circ (am,bp,cm,dp,cin)); :: thesis: for a123x, a123y, a123z being Element of BOOLEAN st a123x = s . [<*(GFA2AdderOutput (am,bp,cm)),cin*>,and2c] & a123y = s . [<*cin,dp*>,and2a] & a123z = s . [<*dp,(GFA2AdderOutput (am,bp,cm))*>,and2] holds
(Following s) . (GFA1CarryOutput ((GFA2AdderOutput (am,bp,cm)),cin,dp)) = (a123x 'or' a123y) 'or' a123z
let a123x, a123y, a123z be Element of BOOLEAN ; :: thesis: ( a123x = s . [<*(GFA2AdderOutput (am,bp,cm)),cin*>,and2c] & a123y = s . [<*cin,dp*>,and2a] & a123z = s . [<*dp,(GFA2AdderOutput (am,bp,cm))*>,and2] implies (Following s) . (GFA1CarryOutput ((GFA2AdderOutput (am,bp,cm)),cin,dp)) = (a123x 'or' a123y) 'or' a123z )
assume A1: ( a123x = s . [<*(GFA2AdderOutput (am,bp,cm)),cin*>,and2c] & a123y = s . [<*cin,dp*>,and2a] & a123z = s . [<*dp,(GFA2AdderOutput (am,bp,cm))*>,and2] ) ; :: thesis: (Following s) . (GFA1CarryOutput ((GFA2AdderOutput (am,bp,cm)),cin,dp)) = (a123x 'or' a123y) 'or' a123z
A2: ( [<*(GFA2AdderOutput (am,bp,cm)),cin*>,and2c] in the carrier of (BitFTA2Str (am,bp,cm,dp,cin)) & [<*cin,dp*>,and2a] in the carrier of (BitFTA2Str (am,bp,cm,dp,cin)) ) by Th24;
A3: ( [<*dp,(GFA2AdderOutput (am,bp,cm))*>,and2] in the carrier of (BitFTA2Str (am,bp,cm,dp,cin)) & dom s = the carrier of (BitFTA2Str (am,bp,cm,dp,cin)) ) by Th24, CIRCUIT1:3;
InnerVertices (BitFTA2Str (am,bp,cm,dp,cin)) = the carrier' of (BitFTA2Str (am,bp,cm,dp,cin)) by FACIRC_1:37;
then GFA1CarryOutput ((GFA2AdderOutput (am,bp,cm)),cin,dp) in the carrier' of (BitFTA2Str (am,bp,cm,dp,cin)) by Th25;
hence (Following s) . (GFA1CarryOutput ((GFA2AdderOutput (am,bp,cm)),cin,dp)) = or3 . (s * <*[<*(GFA2AdderOutput (am,bp,cm)),cin*>,and2c],[<*cin,dp*>,and2a],[<*dp,(GFA2AdderOutput (am,bp,cm))*>,and2]*>) by FACIRC_1:35
.= or3 . <*a123x,a123y,a123z*> by A1, A2, A3, FINSEQ_2:126
.= (a123x 'or' a123y) 'or' a123z by FACIRC_1:def 7 ;
:: thesis: verum