let ap, bm, cp, dm be non pair set ; :: thesis: for cin being set
for s being State of (BitFTA1Circ (ap,bm,cp,dm,cin))
for a123, a5 being Element of BOOLEAN st a123 = s . (GFA1AdderOutput (ap,bm,cp)) & a5 = s . cin holds
(Following s) . [<*(GFA1AdderOutput (ap,bm,cp)),cin*>,xor2c] = a123 'xor' ('not' a5)

let cin be set ; :: thesis: for s being State of (BitFTA1Circ (ap,bm,cp,dm,cin))
for a123, a5 being Element of BOOLEAN st a123 = s . (GFA1AdderOutput (ap,bm,cp)) & a5 = s . cin holds
(Following s) . [<*(GFA1AdderOutput (ap,bm,cp)),cin*>,xor2c] = a123 'xor' ('not' a5)

set S = BitFTA1Str (ap,bm,cp,dm,cin);
set C = BitFTA1Circ (ap,bm,cp,dm,cin);
set A1 = GFA1AdderOutput (ap,bm,cp);
set A1cin = [<*(GFA1AdderOutput (ap,bm,cp)),cin*>,xor2c];
let s be State of (BitFTA1Circ (ap,bm,cp,dm,cin)); :: thesis: for a123, a5 being Element of BOOLEAN st a123 = s . (GFA1AdderOutput (ap,bm,cp)) & a5 = s . cin holds
(Following s) . [<*(GFA1AdderOutput (ap,bm,cp)),cin*>,xor2c] = a123 'xor' ('not' a5)

let a123, a5 be Element of BOOLEAN ; :: thesis: ( a123 = s . (GFA1AdderOutput (ap,bm,cp)) & a5 = s . cin implies (Following s) . [<*(GFA1AdderOutput (ap,bm,cp)),cin*>,xor2c] = a123 'xor' ('not' a5) )
assume A1: ( a123 = s . (GFA1AdderOutput (ap,bm,cp)) & a5 = s . cin ) ; :: thesis: (Following s) . [<*(GFA1AdderOutput (ap,bm,cp)),cin*>,xor2c] = a123 'xor' ('not' a5)
A2: dom s = the carrier of (BitFTA1Str (ap,bm,cp,dm,cin)) by CIRCUIT1:3;
A3: ( GFA1AdderOutput (ap,bm,cp) in the carrier of (BitFTA1Str (ap,bm,cp,dm,cin)) & cin in the carrier of (BitFTA1Str (ap,bm,cp,dm,cin)) ) by Th14;
InnerVertices (BitFTA1Str (ap,bm,cp,dm,cin)) = the carrier' of (BitFTA1Str (ap,bm,cp,dm,cin)) by FACIRC_1:37;
then [<*(GFA1AdderOutput (ap,bm,cp)),cin*>,xor2c] in the carrier' of (BitFTA1Str (ap,bm,cp,dm,cin)) by Th15;
hence (Following s) . [<*(GFA1AdderOutput (ap,bm,cp)),cin*>,xor2c] = xor2c . (s * <*(GFA1AdderOutput (ap,bm,cp)),cin*>) by FACIRC_1:35
.= xor2c . <*a123,a5*> by A1, A3, A2, FINSEQ_2:125
.= a123 'xor' ('not' a5) by GFACIRC1:def 4 ;
:: thesis: verum