let ap, bm, cp, dm be non pair set ; :: thesis: for cin being set st cin <> [<*dm,(GFA1AdderOutput (ap,bm,cp))*>,nor2] & not cin in InnerVertices (BitGFA1Str (ap,bm,cp)) holds
for s being State of (BitFTA1Circ (ap,bm,cp,dm,cin))
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bm & a3 = s . cp & a4 = s . dm & a5 = s . cin holds
( (Following (s,2)) . (GFA1AdderOutput (ap,bm,cp)) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) & (Following (s,2)) . ap = a1 & (Following (s,2)) . bm = a2 & (Following (s,2)) . cp = a3 & (Following (s,2)) . dm = a4 & (Following (s,2)) . cin = a5 )
let cin be set ; :: thesis: ( cin <> [<*dm,(GFA1AdderOutput (ap,bm,cp))*>,nor2] & not cin in InnerVertices (BitGFA1Str (ap,bm,cp)) implies for s being State of (BitFTA1Circ (ap,bm,cp,dm,cin))
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bm & a3 = s . cp & a4 = s . dm & a5 = s . cin holds
( (Following (s,2)) . (GFA1AdderOutput (ap,bm,cp)) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) & (Following (s,2)) . ap = a1 & (Following (s,2)) . bm = a2 & (Following (s,2)) . cp = a3 & (Following (s,2)) . dm = a4 & (Following (s,2)) . cin = a5 ) )
assume A1: ( cin <> [<*dm,(GFA1AdderOutput (ap,bm,cp))*>,nor2] & not cin in InnerVertices (BitGFA1Str (ap,bm,cp)) ) ; :: thesis: for s being State of (BitFTA1Circ (ap,bm,cp,dm,cin))
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bm & a3 = s . cp & a4 = s . dm & a5 = s . cin holds
( (Following (s,2)) . (GFA1AdderOutput (ap,bm,cp)) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) & (Following (s,2)) . ap = a1 & (Following (s,2)) . bm = a2 & (Following (s,2)) . cp = a3 & (Following (s,2)) . dm = a4 & (Following (s,2)) . cin = a5 )
set A1 = GFA1AdderOutput (ap,bm,cp);
set C1 = BitGFA1Circ (ap,bm,cp);
set S1 = BitGFA1Str (ap,bm,cp);
set S2 = BitGFA2Str ((GFA1AdderOutput (ap,bm,cp)),cin,dm);
set C2 = BitGFA2Circ ((GFA1AdderOutput (ap,bm,cp)),cin,dm);
set S = BitFTA1Str (ap,bm,cp,dm,cin);
let s be State of (BitFTA1Circ (ap,bm,cp,dm,cin)); :: thesis: for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bm & a3 = s . cp & a4 = s . dm & a5 = s . cin holds
( (Following (s,2)) . (GFA1AdderOutput (ap,bm,cp)) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) & (Following (s,2)) . ap = a1 & (Following (s,2)) . bm = a2 & (Following (s,2)) . cp = a3 & (Following (s,2)) . dm = a4 & (Following (s,2)) . cin = a5 )
let a1, a2, a3, a4, a5 be Element of BOOLEAN ; :: thesis: ( a1 = s . ap & a2 = s . bm & a3 = s . cp & a4 = s . dm & a5 = s . cin implies ( (Following (s,2)) . (GFA1AdderOutput (ap,bm,cp)) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) & (Following (s,2)) . ap = a1 & (Following (s,2)) . bm = a2 & (Following (s,2)) . cp = a3 & (Following (s,2)) . dm = a4 & (Following (s,2)) . cin = a5 ) )
assume that
A2: a1 = s . ap and
A3: a2 = s . bm and
A4: a3 = s . cp and
A5: a4 = s . dm and
A6: a5 = s . cin ; :: thesis: ( (Following (s,2)) . (GFA1AdderOutput (ap,bm,cp)) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) & (Following (s,2)) . ap = a1 & (Following (s,2)) . bm = a2 & (Following (s,2)) . cp = a3 & (Following (s,2)) . dm = a4 & (Following (s,2)) . cin = a5 )
reconsider s1 = s | the carrier of (BitGFA1Str (ap,bm,cp)) as State of (BitGFA1Circ (ap,bm,cp)) by FACIRC_1:26;
A7: dom s1 = the carrier of (BitGFA1Str (ap,bm,cp)) by CIRCUIT1:3;
A8: dm in InputVertices (BitFTA1Str (ap,bm,cp,dm,cin)) by A1, Th16;
then A9: (Following s) . dm = a4 by A5, CIRCUIT2:def 5;
A10: cp in InputVertices (BitFTA1Str (ap,bm,cp,dm,cin)) by A1, Th16;
then A11: (Following s) . cp = a3 by A4, CIRCUIT2:def 5;
bm in the carrier of (BitGFA1Str (ap,bm,cp)) by GFACIRC1:68;
then A12: a2 = s1 . bm by A3, A7, FUNCT_1:47;
reconsider t = s as State of ((BitGFA1Circ (ap,bm,cp)) +* (BitGFA2Circ ((GFA1AdderOutput (ap,bm,cp)),cin,dm))) ;
( GFA1AdderOutput (ap,bm,cp) in the carrier of (BitGFA1Str (ap,bm,cp)) & InputVertices (BitGFA1Str (ap,bm,cp)) misses InnerVertices (BitGFA2Str ((GFA1AdderOutput (ap,bm,cp)),cin,dm)) ) by Lm12, GFACIRC1:68;
then A13: (Following (t,2)) . (GFA1AdderOutput (ap,bm,cp)) = (Following (s1,2)) . (GFA1AdderOutput (ap,bm,cp)) by FACIRC_1:32;
cp in the carrier of (BitGFA1Str (ap,bm,cp)) by GFACIRC1:68;
then A14: a3 = s1 . cp by A4, A7, FUNCT_1:47;
ap in the carrier of (BitGFA1Str (ap,bm,cp)) by GFACIRC1:68;
then a1 = s1 . ap by A2, A7, FUNCT_1:47;
hence (Following (s,2)) . (GFA1AdderOutput (ap,bm,cp)) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) by A12, A14, A13, GFACIRC1:71; :: thesis: ( (Following (s,2)) . ap = a1 & (Following (s,2)) . bm = a2 & (Following (s,2)) . cp = a3 & (Following (s,2)) . dm = a4 & (Following (s,2)) . cin = a5 )
A15: bm in InputVertices (BitFTA1Str (ap,bm,cp,dm,cin)) by A1, Th16;
then A16: (Following s) . bm = a2 by A3, CIRCUIT2:def 5;
A17: cin in InputVertices (BitFTA1Str (ap,bm,cp,dm,cin)) by A1, Th16;
then A18: (Following s) . cin = a5 by A6, CIRCUIT2:def 5;
A19: ap in InputVertices (BitFTA1Str (ap,bm,cp,dm,cin)) by A1, Th16;
then ( Following (s,2) = Following (Following s) & (Following s) . ap = a1 ) by A2, CIRCUIT2:def 5, FACIRC_1:15;
hence ( (Following (s,2)) . ap = a1 & (Following (s,2)) . bm = a2 & (Following (s,2)) . cp = a3 & (Following (s,2)) . dm = a4 & (Following (s,2)) . cin = a5 ) by A19, A15, A10, A8, A17, A16, A11, A9, A18, CIRCUIT2:def 5; :: thesis: verum