let S1, S2 be non empty non void unsplit gate`1=arity gate`2isBoolean ManySortedSign ; :: thesis: ( InnerVertices S2 misses InputVertices S1 implies for A1 being gate`2=den Boolean Circuit of S1

for A2 being gate`2=den Boolean Circuit of S2

for s being State of (A1 +* A2)

for s1 being State of A1 st s1 = s | the carrier of S1 holds

(Following s) | the carrier of S1 = Following s1 )

assume A1: InnerVertices S2 misses InputVertices S1 ; :: thesis: for A1 being gate`2=den Boolean Circuit of S1

for A2 being gate`2=den Boolean Circuit of S2

for s being State of (A1 +* A2)

for s1 being State of A1 st s1 = s | the carrier of S1 holds

(Following s) | the carrier of S1 = Following s1

let A1 be gate`2=den Boolean Circuit of S1; :: thesis: for A2 being gate`2=den Boolean Circuit of S2

for s being State of (A1 +* A2)

for s1 being State of A1 st s1 = s | the carrier of S1 holds

(Following s) | the carrier of S1 = Following s1

let A2 be gate`2=den Boolean Circuit of S2; :: thesis: for s being State of (A1 +* A2)

for s1 being State of A1 st s1 = s | the carrier of S1 holds

(Following s) | the carrier of S1 = Following s1

let s be State of (A1 +* A2); :: thesis: for s1 being State of A1 st s1 = s | the carrier of S1 holds

(Following s) | the carrier of S1 = Following s1

let s1 be State of A1; :: thesis: ( s1 = s | the carrier of S1 implies (Following s) | the carrier of S1 = Following s1 )

assume A2: s1 = s | the carrier of S1 ; :: thesis: (Following s) | the carrier of S1 = Following s1

reconsider s2 = s | the carrier of S2 as State of A2 by Th26;

( dom (Following s1) = the carrier of S1 & Following s = (Following s2) +* (Following s1) ) by A1, A2, CIRCCOMB:33, CIRCCOMB:60, CIRCUIT1:3;

hence (Following s) | the carrier of S1 = Following s1 by FUNCT_4:23; :: thesis: verum

for A2 being gate`2=den Boolean Circuit of S2

for s being State of (A1 +* A2)

for s1 being State of A1 st s1 = s | the carrier of S1 holds

(Following s) | the carrier of S1 = Following s1 )

assume A1: InnerVertices S2 misses InputVertices S1 ; :: thesis: for A1 being gate`2=den Boolean Circuit of S1

for A2 being gate`2=den Boolean Circuit of S2

for s being State of (A1 +* A2)

for s1 being State of A1 st s1 = s | the carrier of S1 holds

(Following s) | the carrier of S1 = Following s1

let A1 be gate`2=den Boolean Circuit of S1; :: thesis: for A2 being gate`2=den Boolean Circuit of S2

for s being State of (A1 +* A2)

for s1 being State of A1 st s1 = s | the carrier of S1 holds

(Following s) | the carrier of S1 = Following s1

let A2 be gate`2=den Boolean Circuit of S2; :: thesis: for s being State of (A1 +* A2)

for s1 being State of A1 st s1 = s | the carrier of S1 holds

(Following s) | the carrier of S1 = Following s1

let s be State of (A1 +* A2); :: thesis: for s1 being State of A1 st s1 = s | the carrier of S1 holds

(Following s) | the carrier of S1 = Following s1

let s1 be State of A1; :: thesis: ( s1 = s | the carrier of S1 implies (Following s) | the carrier of S1 = Following s1 )

assume A2: s1 = s | the carrier of S1 ; :: thesis: (Following s) | the carrier of S1 = Following s1

reconsider s2 = s | the carrier of S2 as State of A2 by Th26;

( dom (Following s1) = the carrier of S1 & Following s = (Following s2) +* (Following s1) ) by A1, A2, CIRCCOMB:33, CIRCCOMB:60, CIRCUIT1:3;

hence (Following s) | the carrier of S1 = Following s1 by FUNCT_4:23; :: thesis: verum