hereby ( ( x `1_3 = 9 implies ex b1 being SCM+FSA-State ex i being Integer ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & i = (s . (x coll_addr1 )) /. k & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),(succ (IC s)) ) ) & ( x `1_3 = 10 implies ex b1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) ) ) & ( x `1_3 = 11 implies ex b1 being SCM+FSA-State st b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr3 ),(len (s . (x coll_addr2 )))),(succ (IC s)) ) & ( x `1_3 = 12 implies ex b1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) ) ) & ( not x `1_3 <= 8 & not x `1_3 = 9 & not x `1_3 = 10 & not x `1_3 = 11 & not x `1_3 = 12 implies ex b1 being SCM+FSA-State st b1 = s ) )
end;
hereby ( ( x `1_3 = 10 implies ex b1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) ) ) & ( x `1_3 = 11 implies ex b1 being SCM+FSA-State st b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr3 ),(len (s . (x coll_addr2 )))),(succ (IC s)) ) & ( x `1_3 = 12 implies ex b1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) ) ) & ( not x `1_3 <= 8 & not x `1_3 = 9 & not x `1_3 = 10 & not x `1_3 = 11 & not x `1_3 = 12 implies ex b1 being SCM+FSA-State st b1 = s ) )
reconsider k =
abs (s . (x int_addr2 )) as
Element of
NAT ;
assume
x `1_3 = 9
;
ex s1 being SCM+FSA-State ex i being Integer ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & i = (s . (x coll_addr1 )) /. k & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),(succ (IC s)) )reconsider i =
(s . (x coll_addr1 )) /. k as
Integer ;
take s1 =
SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),
(succ (IC s));
ex i being Integer ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & i = (s . (x coll_addr1 )) /. k & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),(succ (IC s)) )take i =
i;
ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & i = (s . (x coll_addr1 )) /. k & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),(succ (IC s)) )take k =
k;
( k = abs (s . (x int_addr2 )) & i = (s . (x coll_addr1 )) /. k & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),(succ (IC s)) )thus
(
k = abs (s . (x int_addr2 )) &
i = (s . (x coll_addr1 )) /. k &
s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),
(succ (IC s)) )
;
verum
end;
hereby ( ( x `1_3 = 11 implies ex b1 being SCM+FSA-State st b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr3 ),(len (s . (x coll_addr2 )))),(succ (IC s)) ) & ( x `1_3 = 12 implies ex b1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) ) ) & ( not x `1_3 <= 8 & not x `1_3 = 9 & not x `1_3 = 10 & not x `1_3 = 11 & not x `1_3 = 12 implies ex b1 being SCM+FSA-State st b1 = s ) )
reconsider k =
abs (s . (x int_addr2 )) as
Element of
NAT ;
assume
x `1_3 = 10
;
ex s1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )per cases
( k in dom (s . (x coll_addr1 )) or not k in dom (s . (x coll_addr1 )) )
;
suppose A1:
k in dom (s . (x coll_addr1 ))
;
ex s1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )set f =
(s . (x coll_addr1 )) +* (k .--> (s . (x int_addr1 )));
A2:
{k} c= dom (s . (x coll_addr1 ))
by A1, ZFMISC_1:37;
dom ((s . (x coll_addr1 )) +* (k .--> (s . (x int_addr1 )))) =
(dom (s . (x coll_addr1 ))) \/ (dom (k .--> (s . (x int_addr1 ))))
by FUNCT_4:def 1
.=
(dom (s . (x coll_addr1 ))) \/ {k}
by FUNCOP_1:19
.=
dom (s . (x coll_addr1 ))
by A2, XBOOLE_1:12
.=
Seg (len (s . (x coll_addr1 )))
by FINSEQ_1:def 3
;
then reconsider f =
(s . (x coll_addr1 )) +* (k .--> (s . (x int_addr1 ))) as
FinSequence by FINSEQ_1:def 2;
(
s . (x int_addr1 ) in INT &
rng (k .--> (s . (x int_addr1 ))) = {(s . (x int_addr1 ))} )
by FUNCOP_1:14, INT_1:def 2;
then
(
rng (s . (x coll_addr1 )) c= INT &
rng (k .--> (s . (x int_addr1 ))) c= INT )
by FINSEQ_1:def 4, ZFMISC_1:37;
then
(
rng f c= (rng (s . (x coll_addr1 ))) \/ (rng (k .--> (s . (x int_addr1 )))) &
(rng (s . (x coll_addr1 ))) \/ (rng (k .--> (s . (x int_addr1 )))) c= INT )
by FUNCT_4:18, XBOOLE_1:8;
then
rng f c= INT
by XBOOLE_1:1;
then reconsider f =
f as
FinSequence of
INT by FINSEQ_1:def 4;
take s1 =
SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),
(succ (IC s));
ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )take f =
f;
ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )take k =
k;
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )thus
k = abs (s . (x int_addr2 ))
;
( f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )thus
f = (s . (x coll_addr1 )) +* k,
(s . (x int_addr1 ))
by A1, FUNCT_7:def 3;
s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s))thus
s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),
(succ (IC s))
;
verum end; suppose A3:
not
k in dom (s . (x coll_addr1 ))
;
ex s1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )reconsider f =
s . (x coll_addr1 ) as
FinSequence of
INT ;
take s1 =
SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),
(succ (IC s));
ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )take f =
f;
ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )take k =
k;
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )thus
k = abs (s . (x int_addr2 ))
;
( f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )thus
f = (s . (x coll_addr1 )) +* k,
(s . (x int_addr1 ))
by A3, FUNCT_7:def 3;
s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s))thus
s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),
(succ (IC s))
;
verum end; end;
end;
thus
( x `1_3 = 11 implies ex s1 being SCM+FSA-State st s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr3 ),(len (s . (x coll_addr2 )))),(succ (IC s)) )
; ( ( x `1_3 = 12 implies ex b1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) ) ) & ( not x `1_3 <= 8 & not x `1_3 = 9 & not x `1_3 = 10 & not x `1_3 = 11 & not x `1_3 = 12 implies ex b1 being SCM+FSA-State st b1 = s ) )
hereby ( not x `1_3 <= 8 & not x `1_3 = 9 & not x `1_3 = 10 & not x `1_3 = 11 & not x `1_3 = 12 implies ex b1 being SCM+FSA-State st b1 = s )
reconsider k =
abs (s . (x int_addr3 )) as
Element of
NAT ;
assume
x `1_3 = 12
;
ex s1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) )
0 in INT
by INT_1:def 2;
then A4:
{0 } c= INT
by ZFMISC_1:37;
k |-> 0 = (Seg k) --> 0
by FINSEQ_2:def 2;
then
rng (k |-> 0 ) c= {0 }
by FUNCOP_1:19;
then
rng (k |-> 0 ) c= INT
by A4, XBOOLE_1:1;
then reconsider f =
k |-> 0 as
FinSequence of
INT by FINSEQ_1:def 4;
take s1 =
SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),
(succ (IC s));
ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) )take f =
f;
ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) )take k =
k;
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) )thus
(
k = abs (s . (x int_addr3 )) &
f = k |-> 0 &
s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),
(succ (IC s)) )
;
verum
end;
thus
( not x `1_3 <= 8 & not x `1_3 = 9 & not x `1_3 = 10 & not x `1_3 = 11 & not x `1_3 = 12 implies ex b1 being SCM+FSA-State st b1 = s )
; verum