set f1 = and2 ;
set f2 = and2 ;
set f3 = and2 ;
set f0 = xor2 ;
let x, y, z be set ; :: thesis: ( z <> [<*x,y*>,xor2 ] & x <> [<*y,z*>,and2 ] & y <> [<*z,x*>,and2 ] & z <> [<*x,y*>,and2 ] implies for s being State of (BitGFA0Circ x,y,z)
for a1, a2, a3 being Element of BOOLEAN st a1 = s . x & a2 = s . y & a3 = s . z holds
( (Following s,2) . (GFA0AdderOutput x,y,z) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . (GFA0CarryOutput x,y,z) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) ) )
assume that
A1: z <> [<*x,y*>,xor2 ] and
A2: ( x <> [<*y,z*>,and2 ] & y <> [<*z,x*>,and2 ] & z <> [<*x,y*>,and2 ] ) ; :: thesis: for s being State of (BitGFA0Circ x,y,z)
for a1, a2, a3 being Element of BOOLEAN st a1 = s . x & a2 = s . y & a3 = s . z holds
( (Following s,2) . (GFA0AdderOutput x,y,z) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . (GFA0CarryOutput x,y,z) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) )
set S2 = GFA0CarryStr x,y,z;
set S1 = GFA0AdderStr x,y,z;
InputVertices (GFA0AdderStr x,y,z) = {x,y,z} by A1, FACIRC_1:57;
then A3: InputVertices (GFA0AdderStr x,y,z) = InputVertices (GFA0CarryStr x,y,z) by A2, Th17;
set A2 = GFA0CarryCirc x,y,z;
set A1 = GFA0AdderCirc x,y,z;
set A = BitGFA0Circ x,y,z;
let s be State of (BitGFA0Circ x,y,z); :: thesis: for a1, a2, a3 being Element of BOOLEAN st a1 = s . x & a2 = s . y & a3 = s . z holds
( (Following s,2) . (GFA0AdderOutput x,y,z) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . (GFA0CarryOutput x,y,z) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) )
let a1, a2, a3 be Element of BOOLEAN ; :: thesis: ( a1 = s . x & a2 = s . y & a3 = s . z implies ( (Following s,2) . (GFA0AdderOutput x,y,z) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . (GFA0CarryOutput x,y,z) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) ) )
assume that
A4: a1 = s . x and
A5: a2 = s . y and
A6: a3 = s . z ; :: thesis: ( (Following s,2) . (GFA0AdderOutput x,y,z) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . (GFA0CarryOutput x,y,z) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) )
reconsider s1 = s | the carrier of (GFA0AdderStr x,y,z) as State of (GFA0AdderCirc x,y,z) by FACIRC_1:26;
A7: dom s1 = the carrier of (GFA0AdderStr x,y,z) by CIRCUIT1:4;
z in the carrier of (GFA0AdderStr x,y,z) by FACIRC_1:60;
then A8: a3 = s1 . z by A6, A7, FUNCT_1:70;
y in the carrier of (GFA0AdderStr x,y,z) by FACIRC_1:60;
then A9: a2 = s1 . y by A5, A7, FUNCT_1:70;
reconsider t = s as State of ((GFA0AdderCirc x,y,z) +* (GFA0CarryCirc x,y,z)) ;
InnerVertices (GFA0CarryStr x,y,z) misses InputVertices (GFA0CarryStr x,y,z) by XBOOLE_1:79;
then A10: (Following t,2) . (GFA0AdderOutput x,y,z) = (Following s1,2) . (GFA0AdderOutput x,y,z) by A3, FACIRC_1:32;
reconsider s2 = s | the carrier of (GFA0CarryStr x,y,z) as State of (GFA0CarryCirc x,y,z) by FACIRC_1:26;
A11: dom s2 = the carrier of (GFA0CarryStr x,y,z) by CIRCUIT1:4;
x in the carrier of (GFA0AdderStr x,y,z) by FACIRC_1:60;
then a1 = s1 . x by A4, A7, FUNCT_1:70;
hence (Following s,2) . (GFA0AdderOutput x,y,z) = (a1 'xor' a2) 'xor' a3 by A1, A9, A8, A10, Th37; :: thesis: (Following s,2) . (GFA0CarryOutput x,y,z) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1)
InnerVertices (GFA0AdderStr x,y,z) misses InputVertices (GFA0AdderStr x,y,z) by XBOOLE_1:79;
then A12: (Following t,2) . (GFA0CarryOutput x,y,z) = (Following s2,2) . (GFA0CarryOutput x,y,z) by A3, FACIRC_1:33;
z in the carrier of (GFA0CarryStr x,y,z) by Th19;
then A13: a3 = s2 . z by A6, A11, FUNCT_1:70;
y in the carrier of (GFA0CarryStr x,y,z) by Th19;
then A14: a2 = s2 . y by A5, A11, FUNCT_1:70;
x in the carrier of (GFA0CarryStr x,y,z) by Th19;
then a1 = s2 . x by A4, A11, FUNCT_1:70;
hence (Following s,2) . (GFA0CarryOutput x,y,z) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) by A2, A14, A13, A12, Th25; :: thesis: verum