let ap, bm, cp, dm be non pair set ; :: thesis:
let cin be set ; :: thesis:
assume A1: ( cin <> [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ] & not cin in InnerVertices (BitGFA1Str ap,bm,cp) ) ; :: thesis:
set S = BitFTA1Str ap,bm,cp,dm,cin;
A2: ( ap in InputVertices (BitFTA1Str ap,bm,cp,dm,cin) & bm in InputVertices (BitFTA1Str ap,bm,cp,dm,cin) ) by A1, Th16;
A3: ( cp in InputVertices (BitFTA1Str ap,bm,cp,dm,cin) & dm in InputVertices (BitFTA1Str ap,bm,cp,dm,cin) ) by A1, Th16;
set A1 = GFA1AdderOutput ap,bm,cp;
let s be State of (BitFTA1Circ ap,bm,cp,dm,cin); :: thesis:
set dmA1 = [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ];
let a1, a2, a3, a4, a5 be Element of BOOLEAN ; :: thesis:
assume A4: ( a1 = s . ap & a2 = s . bm & a3 = s . cp & a4 = s . dm & a5 = s . cin ) ; :: thesis:
A5: (Following s,3) . [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ] = ('not' a4) '&' ((a1 'xor' ('not' a2)) 'xor' a3) by A1, A4, Lm15;
set cindm = [<*cin,dm*>,and2c ];
set A1cin = [<*(GFA1AdderOutput ap,bm,cp),cin*>,and2a ];
set A2 = GFA2CarryOutput (GFA1AdderOutput ap,bm,cp),cin,dm;
A6: Following s,(3 + 1) = Following (Following s,3) by FACIRC_1:12;
( (Following s,3) . [<*(GFA1AdderOutput ap,bm,cp),cin*>,and2a ] = ((a1 'xor' ('not' a2)) 'xor' a3) '&' a5 & (Following s,3) . [<*cin,dm*>,and2c ] = a5 '&' ('not' a4) ) by A1, A4, Lm15;
hence (Following s,4) . (GFA2CarryOutput (GFA1AdderOutput ap,bm,cp),cin,dm) = 'not' (((((a1 'xor' ('not' a2)) 'xor' a3) '&' a5) 'or' (a5 '&' ('not' a4))) 'or' (('not' a4) '&' ((a1 'xor' ('not' a2)) 'xor' a3))) by A6, A5, Lm17; :: thesis:
A7: ( (Following s,3) . cp = a3 & (Following s,3) . dm = a4 ) by A1, A4, Lm15;
A8: (Following s,3) . cin = a5 by A1, A4, Lm15;
A9: cin in InputVertices (BitFTA1Str ap,bm,cp,dm,cin) by A1, Th16;
( (Following s,3) . ap = a1 & (Following s,3) . bm = a2 ) by A1, A4, Lm15;
hence ( (Following s,4) . ap = a1 & (Following s,4) . bm = a2 & (Following s,4) . cp = a3 & (Following s,4) . dm = a4 & (Following s,4) . cin = a5 ) by A6, A2, A3, A9, A7, A8, CIRCUIT2:def 5; :: thesis: