let ap, bp, cp, dp be non pair set ; :: thesis:
let cin be set ; :: thesis:
assume A1: ( cin <> [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] & not cin in InnerVertices (BitGFA0Str ap,bp,cp) ) ; :: thesis:
set S = BitFTA0Str ap,bp,cp,dp,cin;
A2: ( ap in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) & bp in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) ) by A1, Th6;
A3: ( cp in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) & dp in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) ) by A1, Th6;
set A1 = GFA0AdderOutput ap,bp,cp;
let s be State of (BitFTA0Circ ap,bp,cp,dp,cin); :: thesis:
set dpA1 = [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ];
let a1, a2, a3, a4, a5 be Element of BOOLEAN ; :: thesis:
assume A4: ( a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin ) ; :: thesis:
A5: (Following s,3) . [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] = a4 '&' ((a1 'xor' a2) 'xor' a3) by A1, A4, Lm5;
set cindp = [<*cin,dp*>,and2 ];
set A1cin = [<*(GFA0AdderOutput ap,bp,cp),cin*>,and2 ];
set A2 = GFA0CarryOutput (GFA0AdderOutput ap,bp,cp),cin,dp;
A6: Following s,(3 + 1) = Following (Following s,3) by FACIRC_1:12;
( (Following s,3) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,and2 ] = ((a1 'xor' a2) 'xor' a3) '&' a5 & (Following s,3) . [<*cin,dp*>,and2 ] = a5 '&' a4 ) by A1, A4, Lm5;
hence (Following s,4) . (GFA0CarryOutput (GFA0AdderOutput ap,bp,cp),cin,dp) = ((((a1 'xor' a2) 'xor' a3) '&' a5) 'or' (a5 '&' a4)) 'or' (a4 '&' ((a1 'xor' a2) 'xor' a3)) by A6, A5, Lm7; :: thesis:
A7: ( (Following s,3) . cp = a3 & (Following s,3) . dp = a4 ) by A1, A4, Lm5;
A8: (Following s,3) . cin = a5 by A1, A4, Lm5;
A9: cin in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) by A1, Th6;
( (Following s,3) . ap = a1 & (Following s,3) . bp = a2 ) by A1, A4, Lm5;
hence ( (Following s,4) . ap = a1 & (Following s,4) . bp = a2 & (Following s,4) . cp = a3 & (Following s,4) . dp = a4 & (Following s,4) . cin = a5 ) by A6, A2, A3, A9, A7, A8, CIRCUIT2:def 5; :: thesis: