let ap, bp, cp, dp be non pair set ; :: thesis: for cin being set st cin <> [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] & not cin in InnerVertices (BitGFA0Str ap,bp,cp) holds
for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin holds
( (Following s,3) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = ((a1 'xor' a2) 'xor' a3) 'xor' a5 & (Following s,3) . ap = a1 & (Following s,3) . bp = a2 & (Following s,3) . cp = a3 & (Following s,3) . dp = a4 & (Following s,3) . cin = a5 )
let cin be set ; :: thesis: ( cin <> [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] & not cin in InnerVertices (BitGFA0Str ap,bp,cp) implies for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin holds
( (Following s,3) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = ((a1 'xor' a2) 'xor' a3) 'xor' a5 & (Following s,3) . ap = a1 & (Following s,3) . bp = a2 & (Following s,3) . cp = a3 & (Following s,3) . dp = a4 & (Following s,3) . cin = a5 ) )
assume A1: ( cin <> [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] & not cin in InnerVertices (BitGFA0Str ap,bp,cp) ) ; :: thesis: for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin holds
( (Following s,3) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = ((a1 'xor' a2) 'xor' a3) 'xor' a5 & (Following s,3) . ap = a1 & (Following s,3) . bp = a2 & (Following s,3) . cp = a3 & (Following s,3) . dp = a4 & (Following s,3) . cin = a5 )
set S = BitFTA0Str ap,bp,cp,dp,cin;
A2: ( ap in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) & bp in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) ) by A1, Th6;
A3: ( cp in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) & dp in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) ) by A1, Th6;
let s be State of (BitFTA0Circ ap,bp,cp,dp,cin); :: thesis: for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin holds
( (Following s,3) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = ((a1 'xor' a2) 'xor' a3) 'xor' a5 & (Following s,3) . ap = a1 & (Following s,3) . bp = a2 & (Following s,3) . cp = a3 & (Following s,3) . dp = a4 & (Following s,3) . cin = a5 )
let a1, a2, a3, a4, a5 be Element of BOOLEAN ; :: thesis: ( a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin implies ( (Following s,3) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = ((a1 'xor' a2) 'xor' a3) 'xor' a5 & (Following s,3) . ap = a1 & (Following s,3) . bp = a2 & (Following s,3) . cp = a3 & (Following s,3) . dp = a4 & (Following s,3) . cin = a5 ) )
assume A4: ( a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin ) ; :: thesis: ( (Following s,3) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = ((a1 'xor' a2) 'xor' a3) 'xor' a5 & (Following s,3) . ap = a1 & (Following s,3) . bp = a2 & (Following s,3) . cp = a3 & (Following s,3) . dp = a4 & (Following s,3) . cin = a5 )
A5: ( (Following s,2) . cp = a3 & (Following s,2) . dp = a4 ) by A1, A4, Th8;
set A1 = GFA0AdderOutput ap,bp,cp;
set A1cin = [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ];
A6: Following s,(2 + 1) = Following (Following s,2) by FACIRC_1:12;
( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . cin = a5 ) by A1, A4, Th8;
hence (Following s,3) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = ((a1 'xor' a2) 'xor' a3) 'xor' a5 by A6, Lm4; :: thesis: ( (Following s,3) . ap = a1 & (Following s,3) . bp = a2 & (Following s,3) . cp = a3 & (Following s,3) . dp = a4 & (Following s,3) . cin = a5 )
A7: (Following s,2) . cin = a5 by A1, A4, Th8;
A8: cin in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) by A1, Th6;
( (Following s,2) . ap = a1 & (Following s,2) . bp = a2 ) by A1, A4, Th8;
hence ( (Following s,3) . ap = a1 & (Following s,3) . bp = a2 & (Following s,3) . cp = a3 & (Following s,3) . dp = a4 & (Following s,3) . cin = a5 ) by A6, A2, A3, A8, A5, A7, CIRCUIT2:def 5; :: thesis: verum