let ap, bp, cp be non pair set ; :: thesis: for dp, cin being set
for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a1, a2, a3 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp holds
( (Following s,2) . (BitFTA0CarryOutput ap,bp,cp,dp,cin) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) & (Following s,2) . (BitFTA0AdderOutputI ap,bp,cp,dp,cin) = (a1 'xor' a2) 'xor' a3 )
let dp, cin be set ; :: thesis: for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a1, a2, a3 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp holds
( (Following s,2) . (BitFTA0CarryOutput ap,bp,cp,dp,cin) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) & (Following s,2) . (BitFTA0AdderOutputI ap,bp,cp,dp,cin) = (a1 'xor' a2) 'xor' a3 )
let s be State of (BitFTA0Circ ap,bp,cp,dp,cin); :: thesis: for a1, a2, a3 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp holds
( (Following s,2) . (BitFTA0CarryOutput ap,bp,cp,dp,cin) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) & (Following s,2) . (BitFTA0AdderOutputI ap,bp,cp,dp,cin) = (a1 'xor' a2) 'xor' a3 )
set S1 = BitGFA0Str ap,bp,cp;
set C1 = BitGFA0Circ ap,bp,cp;
set A1 = GFA0AdderOutput ap,bp,cp;
set A2 = GFA0CarryOutput ap,bp,cp;
set S2 = BitGFA0Str (GFA0AdderOutput ap,bp,cp),cin,dp;
set C2 = BitGFA0Circ (GFA0AdderOutput ap,bp,cp),cin,dp;
let a1, a2, a3 be Element of BOOLEAN ; :: thesis: ( a1 = s . ap & a2 = s . bp & a3 = s . cp implies ( (Following s,2) . (BitFTA0CarryOutput ap,bp,cp,dp,cin) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) & (Following s,2) . (BitFTA0AdderOutputI ap,bp,cp,dp,cin) = (a1 'xor' a2) 'xor' a3 ) )
assume that
A1: a1 = s . ap and
A2: a2 = s . bp and
A3: a3 = s . cp ; :: thesis: ( (Following s,2) . (BitFTA0CarryOutput ap,bp,cp,dp,cin) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) & (Following s,2) . (BitFTA0AdderOutputI ap,bp,cp,dp,cin) = (a1 'xor' a2) 'xor' a3 )
reconsider s1 = s | the carrier of (BitGFA0Str ap,bp,cp) as State of (BitGFA0Circ ap,bp,cp) by FACIRC_1:26;
A4: dom s1 = the carrier of (BitGFA0Str ap,bp,cp) by CIRCUIT1:4;
ap in the carrier of (BitGFA0Str ap,bp,cp) by GFACIRC1:44;
then A5: a1 = s1 . ap by A1, A4, FUNCT_1:70;
reconsider t = s as State of ((BitGFA0Circ ap,bp,cp) +* (BitGFA0Circ (GFA0AdderOutput ap,bp,cp),cin,dp)) ;
A6: InputVertices (BitGFA0Str ap,bp,cp) misses InnerVertices (BitGFA0Str (GFA0AdderOutput ap,bp,cp),cin,dp) by Lm2;
cp in the carrier of (BitGFA0Str ap,bp,cp) by GFACIRC1:44;
then A7: a3 = s1 . cp by A3, A4, FUNCT_1:70;
bp in the carrier of (BitGFA0Str ap,bp,cp) by GFACIRC1:44;
then A8: a2 = s1 . bp by A2, A4, FUNCT_1:70;
GFA0CarryOutput ap,bp,cp in the carrier of (BitGFA0Str ap,bp,cp) by GFACIRC1:44;
then (Following t,2) . (GFA0CarryOutput ap,bp,cp) = (Following s1,2) . (GFA0CarryOutput ap,bp,cp) by A6, FACIRC_1:32;
hence (Following s,2) . (BitFTA0CarryOutput ap,bp,cp,dp,cin) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) by A5, A8, A7, GFACIRC1:47; :: thesis: (Following s,2) . (BitFTA0AdderOutputI ap,bp,cp,dp,cin) = (a1 'xor' a2) 'xor' a3
GFA0AdderOutput ap,bp,cp in the carrier of (BitGFA0Str ap,bp,cp) by GFACIRC1:44;
then (Following t,2) . (GFA0AdderOutput ap,bp,cp) = (Following s1,2) . (GFA0AdderOutput ap,bp,cp) by A6, FACIRC_1:32;
hence (Following s,2) . (BitFTA0AdderOutputI ap,bp,cp,dp,cin) = (a1 'xor' a2) 'xor' a3 by A5, A8, A7, GFACIRC1:47; :: thesis: verum