let am, bm, cm, dm be non pair set ; :: thesis: for cin being set
for s being State of (BitFTA3Circ am,bm,cm,dm,cin)
for a123x, a123y, a123z being Element of BOOLEAN st a123x = s . [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] & a123y = s . [<*cin,dm*>,and2b ] & a123z = s . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] holds
(Following s) . (GFA3CarryOutput (GFA3AdderOutput am,bm,cm),cin,dm) = 'not' ((a123x 'or' a123y) 'or' a123z)
let cin be set ; :: thesis: for s being State of (BitFTA3Circ am,bm,cm,dm,cin)
for a123x, a123y, a123z being Element of BOOLEAN st a123x = s . [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] & a123y = s . [<*cin,dm*>,and2b ] & a123z = s . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] holds
(Following s) . (GFA3CarryOutput (GFA3AdderOutput am,bm,cm),cin,dm) = 'not' ((a123x 'or' a123y) 'or' a123z)
set S = BitFTA3Str am,bm,cm,dm,cin;
set C = BitFTA3Circ am,bm,cm,dm,cin;
set A1 = GFA3AdderOutput am,bm,cm;
set A2 = GFA3CarryOutput (GFA3AdderOutput am,bm,cm),cin,dm;
set A1cin = [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ];
set cindm = [<*cin,dm*>,and2b ];
set dmA1 = [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ];
let s be State of (BitFTA3Circ am,bm,cm,dm,cin); :: thesis: for a123x, a123y, a123z being Element of BOOLEAN st a123x = s . [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] & a123y = s . [<*cin,dm*>,and2b ] & a123z = s . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] holds
(Following s) . (GFA3CarryOutput (GFA3AdderOutput am,bm,cm),cin,dm) = 'not' ((a123x 'or' a123y) 'or' a123z)
let a123x, a123y, a123z be Element of BOOLEAN ; :: thesis: ( a123x = s . [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] & a123y = s . [<*cin,dm*>,and2b ] & a123z = s . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] implies (Following s) . (GFA3CarryOutput (GFA3AdderOutput am,bm,cm),cin,dm) = 'not' ((a123x 'or' a123y) 'or' a123z) )
assume A1: ( a123x = s . [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] & a123y = s . [<*cin,dm*>,and2b ] & a123z = s . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] ) ; :: thesis: (Following s) . (GFA3CarryOutput (GFA3AdderOutput am,bm,cm),cin,dm) = 'not' ((a123x 'or' a123y) 'or' a123z)
A2: ( [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] in the carrier of (BitFTA3Str am,bm,cm,dm,cin) & [<*cin,dm*>,and2b ] in the carrier of (BitFTA3Str am,bm,cm,dm,cin) ) by Th34;
A3: ( [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] in the carrier of (BitFTA3Str am,bm,cm,dm,cin) & dom s = the carrier of (BitFTA3Str am,bm,cm,dm,cin) ) by Th34, CIRCUIT1:4;
InnerVertices (BitFTA3Str am,bm,cm,dm,cin) = the carrier' of (BitFTA3Str am,bm,cm,dm,cin) by FACIRC_1:37;
then GFA3CarryOutput (GFA3AdderOutput am,bm,cm),cin,dm in the carrier' of (BitFTA3Str am,bm,cm,dm,cin) by Th35;
hence (Following s) . (GFA3CarryOutput (GFA3AdderOutput am,bm,cm),cin,dm) = nor3 . (s * <*[<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ],[<*cin,dm*>,and2b ],[<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ]*>) by FACIRC_1:35
.= nor3 . <*a123x,a123y,a123z*> by A1, A2, A3, FINSEQ_2:146
.= 'not' ((a123x 'or' a123y) 'or' a123z) by TWOSCOMP:def 28 ;
:: thesis: verum