let am, bm, cm, dm be non pair set ; :: thesis: for cin being set
for s being State of (BitFTA3Circ am,bm,cm,dm,cin)
for a123, a4, a5 being Element of BOOLEAN st a123 = s . (GFA3AdderOutput am,bm,cm) & a4 = s . dm & a5 = s . cin holds
( (Following s) . [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] = ('not' a123) '&' ('not' a5) & (Following s) . [<*cin,dm*>,and2b ] = ('not' a5) '&' ('not' a4) & (Following s) . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] = ('not' a4) '&' ('not' a123) )
let cin be set ; :: thesis: for s being State of (BitFTA3Circ am,bm,cm,dm,cin)
for a123, a4, a5 being Element of BOOLEAN st a123 = s . (GFA3AdderOutput am,bm,cm) & a4 = s . dm & a5 = s . cin holds
( (Following s) . [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] = ('not' a123) '&' ('not' a5) & (Following s) . [<*cin,dm*>,and2b ] = ('not' a5) '&' ('not' a4) & (Following s) . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] = ('not' a4) '&' ('not' a123) )
set S = BitFTA3Str am,bm,cm,dm,cin;
set C = BitFTA3Circ am,bm,cm,dm,cin;
set A1 = GFA3AdderOutput am,bm,cm;
set S2 = BitGFA3Str (GFA3AdderOutput am,bm,cm),cin,dm;
set C2 = BitGFA3Circ (GFA3AdderOutput am,bm,cm),cin,dm;
set A1cin = [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ];
set cindm = [<*cin,dm*>,and2b ];
set dmA1 = [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ];
let s be State of (BitFTA3Circ am,bm,cm,dm,cin); :: thesis: for a123, a4, a5 being Element of BOOLEAN st a123 = s . (GFA3AdderOutput am,bm,cm) & a4 = s . dm & a5 = s . cin holds
( (Following s) . [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] = ('not' a123) '&' ('not' a5) & (Following s) . [<*cin,dm*>,and2b ] = ('not' a5) '&' ('not' a4) & (Following s) . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] = ('not' a4) '&' ('not' a123) )
let a123, a4, a5 be Element of BOOLEAN ; :: thesis: ( a123 = s . (GFA3AdderOutput am,bm,cm) & a4 = s . dm & a5 = s . cin implies ( (Following s) . [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] = ('not' a123) '&' ('not' a5) & (Following s) . [<*cin,dm*>,and2b ] = ('not' a5) '&' ('not' a4) & (Following s) . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] = ('not' a4) '&' ('not' a123) ) )
assume that
A1: a123 = s . (GFA3AdderOutput am,bm,cm) and
A2: a4 = s . dm and
A3: a5 = s . cin ; :: thesis: ( (Following s) . [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] = ('not' a123) '&' ('not' a5) & (Following s) . [<*cin,dm*>,and2b ] = ('not' a5) '&' ('not' a4) & (Following s) . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] = ('not' a4) '&' ('not' a123) )
A4: dom s = the carrier of (BitFTA3Str am,bm,cm,dm,cin) by CIRCUIT1:4;
A5: cin in the carrier of (BitFTA3Str am,bm,cm,dm,cin) by Th34;
A6: GFA3AdderOutput am,bm,cm in the carrier of (BitFTA3Str am,bm,cm,dm,cin) by Th34;
A7: InnerVertices (BitFTA3Str am,bm,cm,dm,cin) = the carrier' of (BitFTA3Str am,bm,cm,dm,cin) by FACIRC_1:37;
then [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] in the carrier' of (BitFTA3Str am,bm,cm,dm,cin) by Th35;
hence (Following s) . [<*(GFA3AdderOutput am,bm,cm),cin*>,and2b ] = and2b . (s * <*(GFA3AdderOutput am,bm,cm),cin*>) by FACIRC_1:35
.= and2b . <*a123,a5*> by A1, A3, A6, A5, A4, FINSEQ_2:145
.= ('not' a123) '&' ('not' a5) by TWOSCOMP:def 3 ;
:: thesis: ( (Following s) . [<*cin,dm*>,and2b ] = ('not' a5) '&' ('not' a4) & (Following s) . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] = ('not' a4) '&' ('not' a123) )
A8: dm in the carrier of (BitFTA3Str am,bm,cm,dm,cin) by Th34;
[<*cin,dm*>,and2b ] in the carrier' of (BitFTA3Str am,bm,cm,dm,cin) by A7, Th35;
hence (Following s) . [<*cin,dm*>,and2b ] = and2b . (s * <*cin,dm*>) by FACIRC_1:35
.= and2b . <*a5,a4*> by A2, A3, A8, A5, A4, FINSEQ_2:145
.= ('not' a5) '&' ('not' a4) by TWOSCOMP:def 3 ;
:: thesis: (Following s) . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] = ('not' a4) '&' ('not' a123)
[<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] in the carrier' of (BitFTA3Str am,bm,cm,dm,cin) by A7, Th35;
hence (Following s) . [<*dm,(GFA3AdderOutput am,bm,cm)*>,and2b ] = and2b . (s * <*dm,(GFA3AdderOutput am,bm,cm)*>) by FACIRC_1:35
.= and2b . <*a4,a123*> by A1, A2, A6, A8, A4, FINSEQ_2:145
.= ('not' a4) '&' ('not' a123) by TWOSCOMP:def 3 ;
:: thesis: verum