let ap, bp, cp, dp be non pair set ; :: thesis: for cin being set st cin <> [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] & not cin in InnerVertices (BitGFA0Str ap,bp,cp) holds
for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin holds
( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 )
let cin be set ; :: thesis: ( cin <> [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] & not cin in InnerVertices (BitGFA0Str ap,bp,cp) implies for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin holds
( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 ) )
assume A1: ( cin <> [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] & not cin in InnerVertices (BitGFA0Str ap,bp,cp) ) ; :: thesis: for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin holds
( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 )
set A1 = GFA0AdderOutput ap,bp,cp;
set C1 = BitGFA0Circ ap,bp,cp;
set S1 = BitGFA0Str ap,bp,cp;
set S2 = BitGFA0Str (GFA0AdderOutput ap,bp,cp),cin,dp;
set C2 = BitGFA0Circ (GFA0AdderOutput ap,bp,cp),cin,dp;
set S = BitFTA0Str ap,bp,cp,dp,cin;
let s be State of (BitFTA0Circ ap,bp,cp,dp,cin); :: thesis: for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin holds
( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 )
let a1, a2, a3, a4, a5 be Element of BOOLEAN ; :: thesis: ( a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin implies ( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 ) )
assume that
A2: a1 = s . ap and
A3: a2 = s . bp and
A4: a3 = s . cp and
A5: a4 = s . dp and
A6: a5 = s . cin ; :: thesis: ( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 )
reconsider s1 = s | the carrier of (BitGFA0Str ap,bp,cp) as State of (BitGFA0Circ ap,bp,cp) by FACIRC_1:26;
A7: dom s1 = the carrier of (BitGFA0Str ap,bp,cp) by CIRCUIT1:4;
A8: dp in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) by A1, Th6;
then A9: (Following s) . dp = a4 by A5, CIRCUIT2:def 5;
A10: cp in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) by A1, Th6;
then A11: (Following s) . cp = a3 by A4, CIRCUIT2:def 5;
bp in the carrier of (BitGFA0Str ap,bp,cp) by GFACIRC1:44;
then A12: a2 = s1 . bp by A3, A7, FUNCT_1:70;
reconsider t = s as State of ((BitGFA0Circ ap,bp,cp) +* (BitGFA0Circ (GFA0AdderOutput ap,bp,cp),cin,dp)) ;
( GFA0AdderOutput ap,bp,cp in the carrier of (BitGFA0Str ap,bp,cp) & InputVertices (BitGFA0Str ap,bp,cp) misses InnerVertices (BitGFA0Str (GFA0AdderOutput ap,bp,cp),cin,dp) ) by Lm2, GFACIRC1:44;
then A13: (Following t,2) . (GFA0AdderOutput ap,bp,cp) = (Following s1,2) . (GFA0AdderOutput ap,bp,cp) by FACIRC_1:32;
cp in the carrier of (BitGFA0Str ap,bp,cp) by GFACIRC1:44;
then A14: a3 = s1 . cp by A4, A7, FUNCT_1:70;
ap in the carrier of (BitGFA0Str ap,bp,cp) by GFACIRC1:44;
then a1 = s1 . ap by A2, A7, FUNCT_1:70;
hence (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 by A12, A14, A13, GFACIRC1:47; :: thesis: ( (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 )
A15: bp in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) by A1, Th6;
then A16: (Following s) . bp = a2 by A3, CIRCUIT2:def 5;
A17: cin in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) by A1, Th6;
then A18: (Following s) . cin = a5 by A6, CIRCUIT2:def 5;
A19: ap in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) by A1, Th6;
then ( Following s,2 = Following (Following s) & (Following s) . ap = a1 ) by A2, CIRCUIT2:def 5, FACIRC_1:15;
hence ( (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 ) by A19, A15, A10, A8, A17, A16, A11, A9, A18, CIRCUIT2:def 5; :: thesis: verum