let x, y, c be set ; :: thesis: ( x <> [<*y,c*>,'&' ] & y <> [<*c,x*>,'&' ] & c <> [<*x,y*>,'&' ] & c <> [<*x,y*>,'xor' ] implies for s being State of (BitAdderWithOverflowCirc x,y,c) holds Following s,2 is stable )
assume that
A1: x <> [<*y,c*>,'&' ] and
A2: y <> [<*c,x*>,'&' ] and
A3: c <> [<*x,y*>,'&' ] and
A4: c <> [<*x,y*>,'xor' ] ; :: thesis: for s being State of (BitAdderWithOverflowCirc x,y,c) holds Following s,2 is stable
set S = BitAdderWithOverflowStr x,y,c;
set S1 = 2GatesCircStr x,y,c,'xor' ;
set S2 = MajorityStr x,y,c;
set A = BitAdderWithOverflowCirc x,y,c;
set A1 = BitAdderCirc x,y,c;
set A2 = MajorityCirc x,y,c;
let s be State of (BitAdderWithOverflowCirc x,y,c); :: thesis: Following s,2 is stable
reconsider s1 = s | the carrier of (2GatesCircStr x,y,c,'xor' ) as State of (BitAdderCirc x,y,c) by FACIRC_1:26;
reconsider s2 = s | the carrier of (MajorityStr x,y,c) as State of (MajorityCirc x,y,c) by FACIRC_1:26;
reconsider t = s as State of ((BitAdderCirc x,y,c) +* (MajorityCirc x,y,c)) ;
InputVertices (2GatesCircStr x,y,c,'xor' ) = {x,y,c} by A4, FACIRC_1:57;
then A5: InputVertices (2GatesCircStr x,y,c,'xor' ) = InputVertices (MajorityStr x,y,c) by A1, A2, A3, Th21;
A6: InnerVertices (2GatesCircStr x,y,c,'xor' ) misses InputVertices (2GatesCircStr x,y,c,'xor' ) by XBOOLE_1:79;
A7: InnerVertices (MajorityStr x,y,c) misses InputVertices (MajorityStr x,y,c) by XBOOLE_1:79;
then A8: Following s1,2 = (Following t,2) | the carrier of (2GatesCircStr x,y,c,'xor' ) by A5, FACIRC_1:30;
A9: Following s1,3 = (Following t,3) | the carrier of (2GatesCircStr x,y,c,'xor' ) by A5, A7, FACIRC_1:30;
A10: Following s2,2 = (Following t,2) | the carrier of (MajorityStr x,y,c) by A5, A6, FACIRC_1:31;
A11: Following s2,3 = (Following t,3) | the carrier of (MajorityStr x,y,c) by A5, A6, FACIRC_1:31;
Following s1,2 is stable by A4, FACIRC_1:63;
then A12: Following s1,2 = Following (Following s1,2) by CIRCUIT2:def 6
.= Following s1,(2 + 1) by FACIRC_1:12 ;
Following s2,2 is stable by A1, A2, A3, Th30;
then A13: Following s2,2 = Following (Following s2,2) by CIRCUIT2:def 6
.= Following s2,(2 + 1) by FACIRC_1:12 ;
A14: Following s,(2 + 1) = Following (Following s,2) by FACIRC_1:12;
A15: dom (Following s,2) = the carrier of (BitAdderWithOverflowStr x,y,c) by CIRCUIT1:4;
A16: dom (Following s,3) = the carrier of (BitAdderWithOverflowStr x,y,c) by CIRCUIT1:4;
A17: dom (Following s1,2) = the carrier of (2GatesCircStr x,y,c,'xor' ) by CIRCUIT1:4;
A18: dom (Following s2,2) = the carrier of (MajorityStr x,y,c) by CIRCUIT1:4;
A19: the carrier of (BitAdderWithOverflowStr x,y,c) = the carrier of (2GatesCircStr x,y,c,'xor' ) \/ the carrier of (MajorityStr x,y,c) by CIRCCOMB:def 2;

now

let a be set ; :: thesis: ( a in the carrier of (BitAdderWithOverflowStr x,y,c) implies (Following s,2) . a = (Following (Following s,2)) . a )
assume a in the carrier of (BitAdderWithOverflowStr x,y,c) ; :: thesis: (Following s,2) . a = (Following (Following s,2)) . a
then ( a in the carrier of (2GatesCircStr x,y,c,'xor' ) or a in the carrier of (MajorityStr x,y,c) ) by A19, XBOOLE_0:def 3;
then ( ( (Following s,2) . a = (Following s1,2) . a & (Following s,3) . a = (Following s1,3) . a ) or ( (Following s,2) . a = (Following s2,2) . a & (Following s,3) . a = (Following s2,3) . a ) ) by A8, A9, A10, A11, A12, A13, A17, A18, FUNCT_1:70;
hence (Following s,2) . a = (Following (Following s,2)) . a by A12, A13, FACIRC_1:12; :: thesis: verum

end;

hence Following s,2 = Following (Following s,2) by A14, A15, A16, FUNCT_1:9; :: according to CIRCUIT2:def 6 :: thesis: verum