let S1, S2 be non empty non void unsplit gate`1=arity gate`2isBoolean ManySortedSign ; :: thesis: ( InnerVertices S1 misses InputVertices S2 implies for A1 being gate`2=den Boolean Circuit of gate`2=den Boolean
for A2 being gate`2=den Boolean Circuit of gate`2=den Boolean
for s being State of
for s2 being State of st s2 = s | the carrier of S2 holds
(Following s) | the carrier of S2 = Following s2 )
assume A1: InnerVertices S1 misses InputVertices S2 ; :: thesis: for A1 being gate`2=den Boolean Circuit of gate`2=den Boolean
for A2 being gate`2=den Boolean Circuit of gate`2=den Boolean
for s being State of
for s2 being State of st s2 = s | the carrier of S2 holds
(Following s) | the carrier of S2 = Following s2
let A1 be gate`2=den Boolean Circuit of gate`2=den Boolean ; :: thesis: for A2 being gate`2=den Boolean Circuit of gate`2=den Boolean
for s being State of
for s2 being State of st s2 = s | the carrier of S2 holds
(Following s) | the carrier of S2 = Following s2
let A2 be gate`2=den Boolean Circuit of gate`2=den Boolean ; :: thesis: for s being State of
for s2 being State of st s2 = s | the carrier of S2 holds
(Following s) | the carrier of S2 = Following s2
let s be State of ; :: thesis: for s2 being State of st s2 = s | the carrier of S2 holds
(Following s) | the carrier of S2 = Following s2
let s2 be State of ; :: thesis: ( s2 = s | the carrier of S2 implies (Following s) | the carrier of S2 = Following s2 )
assume A2: s2 = s | the carrier of S2 ; :: thesis: (Following s) | the carrier of S2 = Following s2
reconsider s1 = s | the carrier of S1 as State of by Th26;
( dom (Following s2) = the carrier of S2 & Following s = (Following s1) +* (Following s2) ) by A1, A2, CIRCCOMB:39, CIRCCOMB:68, CIRCUIT1:4;
hence (Following s) | the carrier of S2 = Following s2 by FUNCT_4:24; :: thesis: verum