let S1, S2 be non empty non void unsplit gate`1=arity gate`2isBoolean ManySortedSign ; :: thesis: ( InnerVertices S2 misses InputVertices S1 implies for A1 being gate`2=den Boolean Circuit of gate`2=den Boolean
for A2 being gate`2=den Boolean Circuit of gate`2=den Boolean
for s being State of
for s1 being State of st s1 = s | the carrier of S1 holds
(Following s) | the carrier of S1 = Following s1 )
assume A1: InnerVertices S2 misses InputVertices S1 ; :: thesis: for A1 being gate`2=den Boolean Circuit of gate`2=den Boolean
for A2 being gate`2=den Boolean Circuit of gate`2=den Boolean
for s being State of
for s1 being State of st s1 = s | the carrier of S1 holds
(Following s) | the carrier of S1 = Following s1
let A1 be gate`2=den Boolean Circuit of gate`2=den Boolean ; :: thesis: for A2 being gate`2=den Boolean Circuit of gate`2=den Boolean
for s being State of
for s1 being State of st s1 = s | the carrier of S1 holds
(Following s) | the carrier of S1 = Following s1
let A2 be gate`2=den Boolean Circuit of gate`2=den Boolean ; :: thesis: for s being State of
for s1 being State of st s1 = s | the carrier of S1 holds
(Following s) | the carrier of S1 = Following s1
let s be State of ; :: thesis: for s1 being State of st s1 = s | the carrier of S1 holds
(Following s) | the carrier of S1 = Following s1
let s1 be State of ; :: thesis: ( s1 = s | the carrier of S1 implies (Following s) | the carrier of S1 = Following s1 )
assume A2: s1 = s | the carrier of S1 ; :: thesis: (Following s) | the carrier of S1 = Following s1
reconsider s2 = s | the carrier of S2 as State of by Th26;
( dom (Following s1) = the carrier of S1 & Following s = (Following s2) +* (Following s1) ) by A1, A2, CIRCCOMB:40, CIRCCOMB:68, CIRCUIT1:4;
hence (Following s) | the carrier of S1 = Following s1 by FUNCT_4:24; :: thesis: verum