let V be RealLinearSpace; :: thesis: for w, y, u, v being VECTOR of V st Gen w,y holds
u,v,u,v are_DTr_wrt w,y
let w, y, u, v be VECTOR of V; :: thesis: ( Gen w,y implies u,v,u,v are_DTr_wrt w,y )
assume Gen w,y ; :: thesis: u,v,u,v are_DTr_wrt w,y
then ( u,v // u,v & u,v,u # v,u # v are_Ort_wrt w,y ) by Lm6, ANALOAF:17;
hence u,v,u,v are_DTr_wrt w,y by Def3; :: thesis: verum