hereby :: thesis: ( ( InsCode x = 9 implies ex b1 being SCM+FSA-State ex i being Integer ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & i = (s . (x coll_addr1 )) /. k & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),(succ (IC s)) ) ) & ( InsCode x = 10 implies ex b1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) ) ) & ( InsCode x = 11 implies ex b1 being SCM+FSA-State st b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr3 ),(len (s . (x coll_addr2 )))),(succ (IC s)) ) & ( InsCode x = 12 implies ex b1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) ) ) & ( not InsCode x <= 8 & not InsCode x = 9 & not InsCode x = 10 & not InsCode x = 11 & not InsCode x = 12 implies ex b1 being SCM+FSA-State st b1 = s ) )
assume InsCode x <= 8 ; :: thesis: ex s1 being SCM+FSA-State ex x' being Element of SCM-Instr ex s' being SCM-State st
( x = x' & s' = (s | SCM-Memory ) +* (NAT --> x') & s1 = (s +* (SCM-Exec-Res x',s')) +* (s | NAT ) )

then reconsider x' = x as Element of SCM-Instr by Th3;
reconsider s' = (s | SCM-Memory ) +* (NAT --> x') as SCM-State by Th18;
reconsider s1 = (s +* (SCM-Exec-Res x',s')) +* (s | NAT ) as SCM+FSA-State by Th19;
take s1 = s1; :: thesis: ex x' being Element of SCM-Instr ex s' being SCM-State st
( x = x' & s' = (s | SCM-Memory ) +* (NAT --> x') & s1 = (s +* (SCM-Exec-Res x',s')) +* (s | NAT ) )

take x' = x'; :: thesis: ex s' being SCM-State st
( x = x' & s' = (s | SCM-Memory ) +* (NAT --> x') & s1 = (s +* (SCM-Exec-Res x',s')) +* (s | NAT ) )

take s' = s'; :: thesis: ( x = x' & s' = (s | SCM-Memory ) +* (NAT --> x') & s1 = (s +* (SCM-Exec-Res x',s')) +* (s | NAT ) )
thus x = x' ; :: thesis: ( s' = (s | SCM-Memory ) +* (NAT --> x') & s1 = (s +* (SCM-Exec-Res x',s')) +* (s | NAT ) )
thus s' = (s | SCM-Memory ) +* (NAT --> x') ; :: thesis: s1 = (s +* (SCM-Exec-Res x',s')) +* (s | NAT )
thus s1 = (s +* (SCM-Exec-Res x',s')) +* (s | NAT ) ; :: thesis: verum
end;
hereby :: thesis: ( ( InsCode x = 10 implies ex b1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) ) ) & ( InsCode x = 11 implies ex b1 being SCM+FSA-State st b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr3 ),(len (s . (x coll_addr2 )))),(succ (IC s)) ) & ( InsCode x = 12 implies ex b1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) ) ) & ( not InsCode x <= 8 & not InsCode x = 9 & not InsCode x = 10 & not InsCode x = 11 & not InsCode x = 12 implies ex b1 being SCM+FSA-State st b1 = s ) )
assume InsCode x = 9 ; :: thesis: ex s1 being SCM+FSA-State ex i being Integer ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & i = (s . (x coll_addr1 )) /. k & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),(succ (IC s)) )

reconsider k = abs (s . (x int_addr2 )) as Element of NAT ;
reconsider i = (s . (x coll_addr1 )) /. k as Integer ;
take s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),(succ (IC s)); :: thesis: ex i being Integer ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & i = (s . (x coll_addr1 )) /. k & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),(succ (IC s)) )

take i = i; :: thesis: ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & i = (s . (x coll_addr1 )) /. k & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),(succ (IC s)) )

take k = k; :: thesis: ( k = abs (s . (x int_addr2 )) & i = (s . (x coll_addr1 )) /. k & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),(succ (IC s)) )
thus ( k = abs (s . (x int_addr2 )) & i = (s . (x coll_addr1 )) /. k & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr1 ),i),(succ (IC s)) ) ; :: thesis: verum
end;
hereby :: thesis: ( ( InsCode x = 11 implies ex b1 being SCM+FSA-State st b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr3 ),(len (s . (x coll_addr2 )))),(succ (IC s)) ) & ( InsCode x = 12 implies ex b1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) ) ) & ( not InsCode x <= 8 & not InsCode x = 9 & not InsCode x = 10 & not InsCode x = 11 & not InsCode x = 12 implies ex b1 being SCM+FSA-State st b1 = s ) )
assume InsCode x = 10 ; :: thesis: ex s1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )

reconsider k = abs (s . (x int_addr2 )) as Element of NAT ;
per cases ( k in dom (s . (x coll_addr1 )) or not k in dom (s . (x coll_addr1 )) ) ;
suppose A1: k in dom (s . (x coll_addr1 )) ; :: thesis: ex s1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )

then A2: {k} c= dom (s . (x coll_addr1 )) by ZFMISC_1:37;
set f = (s . (x coll_addr1 )) +* (k .--> (s . (x int_addr1 )));
dom ((s . (x coll_addr1 )) +* (k .--> (s . (x int_addr1 )))) = (dom (s . (x coll_addr1 ))) \/ (dom (k .--> (s . (x int_addr1 )))) by FUNCT_4:def 1
.= (dom (s . (x coll_addr1 ))) \/ {k} by FUNCOP_1:19
.= dom (s . (x coll_addr1 )) by A2, XBOOLE_1:12
.= Seg (len (s . (x coll_addr1 ))) by FINSEQ_1:def 3 ;
then reconsider f = (s . (x coll_addr1 )) +* (k .--> (s . (x int_addr1 ))) as FinSequence by FINSEQ_1:def 2;
A3: rng f c= (rng (s . (x coll_addr1 ))) \/ (rng (k .--> (s . (x int_addr1 )))) by FUNCT_4:18;
A4: rng (s . (x coll_addr1 )) c= INT by FINSEQ_1:def 4;
A5: s . (x int_addr1 ) in INT by INT_1:def 2;
rng (k .--> (s . (x int_addr1 ))) = {(s . (x int_addr1 ))} by FUNCOP_1:14;
then rng (k .--> (s . (x int_addr1 ))) c= INT by A5, ZFMISC_1:37;
then (rng (s . (x coll_addr1 ))) \/ (rng (k .--> (s . (x int_addr1 )))) c= INT by A4, XBOOLE_1:8;
then rng f c= INT by A3, XBOOLE_1:1;
then reconsider f = f as FinSequence of INT by FINSEQ_1:def 4;
take s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)); :: thesis: ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )

take f = f; :: thesis: ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )

take k = k; :: thesis: ( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )
thus k = abs (s . (x int_addr2 )) ; :: thesis: ( f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )
thus f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) by A1, FUNCT_7:def 3; :: thesis: s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s))
thus s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) ; :: thesis: verum
end;
suppose A6: not k in dom (s . (x coll_addr1 )) ; :: thesis: ex s1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )

reconsider f = s . (x coll_addr1 ) as FinSequence of INT ;
take s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)); :: thesis: ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )

take f = f; :: thesis: ex k being Element of NAT st
( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )

take k = k; :: thesis: ( k = abs (s . (x int_addr2 )) & f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )
thus k = abs (s . (x int_addr2 )) ; :: thesis: ( f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) )
thus f = (s . (x coll_addr1 )) +* k,(s . (x int_addr1 )) by A6, FUNCT_7:def 3; :: thesis: s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s))
thus s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr1 ),f),(succ (IC s)) ; :: thesis: verum
end;
end;
end;
thus ( InsCode x = 11 implies ex s1 being SCM+FSA-State st s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x int_addr3 ),(len (s . (x coll_addr2 )))),(succ (IC s)) ) ; :: thesis: ( ( InsCode x = 12 implies ex b1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & b1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) ) ) & ( not InsCode x <= 8 & not InsCode x = 9 & not InsCode x = 10 & not InsCode x = 11 & not InsCode x = 12 implies ex b1 being SCM+FSA-State st b1 = s ) )

hereby :: thesis: ( not InsCode x <= 8 & not InsCode x = 9 & not InsCode x = 10 & not InsCode x = 11 & not InsCode x = 12 implies ex b1 being SCM+FSA-State st b1 = s )
assume InsCode x = 12 ; :: thesis: ex s1 being SCM+FSA-State ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) )

reconsider k = abs (s . (x int_addr3 )) as Element of NAT ;
k |-> 0 = (Seg k) --> 0 by FINSEQ_2:def 2;
then A7: rng (k |-> 0 ) c= {0 } by FUNCOP_1:19;
0 in INT by INT_1:def 2;
then {0 } c= INT by ZFMISC_1:37;
then rng (k |-> 0 ) c= INT by A7, XBOOLE_1:1;
then reconsider f = k |-> 0 as FinSequence of INT by FINSEQ_1:def 4;
take s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)); :: thesis: ex f being FinSequence of INT ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) )

take f = f; :: thesis: ex k being Element of NAT st
( k = abs (s . (x int_addr3 )) & f = k |-> 0 & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) )

take k = k; :: thesis: ( k = abs (s . (x int_addr3 )) & f = k |-> 0 & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) )
thus ( k = abs (s . (x int_addr3 )) & f = k |-> 0 & s1 = SCM+FSA-Chg (SCM+FSA-Chg s,(x coll_addr2 ),f),(succ (IC s)) ) ; :: thesis: verum
end;
thus ( not InsCode x <= 8 & not InsCode x = 9 & not InsCode x = 10 & not InsCode x = 11 & not InsCode x = 12 implies ex b1 being SCM+FSA-State st b1 = s ) ; :: thesis: verum