let s be State of SCM+FSA ; :: thesis: ( s . (intloc 0 ) = 1 & IC s = insloc 0 implies Initialize s = s )
assume A1: s . (intloc 0 ) = 1 ; :: thesis: ( not IC s = insloc 0 or Initialize s = s )
assume A2: IC s = insloc 0 ; :: thesis: Initialize s = s
A3: ( intloc 0 in dom s & IC SCM+FSA in dom s ) by AMI_1:94, SCMFSA_2:66;
thus Initialize s = (s +* ((intloc 0 ) .--> 1)) +* (Start-At (insloc 0 )) by SCMFSA6C:def 3
.= s +* ((IC SCM+FSA ) .--> (insloc 0 )) by A1, A3, FUNCT_7:111
.= s by A2, A3, FUNCT_7:111 ; :: thesis: verum