let V be RealLinearSpace; :: thesis: for w, y, u, u1, v, v1, v2 being VECTOR of V st Gen w,y & u <> u1 & u,u1,v,v1 are_DTr_wrt w,y & ( u,u1,v,v2 are_DTr_wrt w,y or u,u1,v2,v are_DTr_wrt w,y ) holds
v1 = v2
let w, y, u, u1, v, v1, v2 be VECTOR of V; :: thesis: ( Gen w,y & u <> u1 & u,u1,v,v1 are_DTr_wrt w,y & ( u,u1,v,v2 are_DTr_wrt w,y or u,u1,v2,v are_DTr_wrt w,y ) implies v1 = v2 )
assume that
A1:
( Gen w,y & u <> u1 & u,u1,v,v1 are_DTr_wrt w,y )
and
A2:
( u,u1,v,v2 are_DTr_wrt w,y or u,u1,v2,v are_DTr_wrt w,y )
; :: thesis: v1 = v2
now assume
u,
u1,
v2,
v are_DTr_wrt w,
y
;
:: thesis: v1 = v2then
v2,
v,
v,
v1 are_DTr_wrt w,
y
by A1, Th21;
then
(
v = v2 &
v = v1 )
by A1, Th20;
hence
v1 = v2
;
:: thesis: verum end;
hence
v1 = v2
by A1, A2, Th26; :: thesis: verum