let ap, bm, cp, dm be non pair set ; :: thesis: for cin being set
for s being State of (BitFTA1Circ ap,bm,cp,dm,cin)
for a123x, a123y, a123z being Element of BOOLEAN st a123x = s . [<*(GFA1AdderOutput ap,bm,cp),cin*>,and2a ] & a123y = s . [<*cin,dm*>,and2c ] & a123z = s . [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ] holds
(Following s) . (GFA2CarryOutput (GFA1AdderOutput ap,bm,cp),cin,dm) = 'not' ((a123x 'or' a123y) 'or' a123z)
let cin be set ; :: thesis: for s being State of (BitFTA1Circ ap,bm,cp,dm,cin)
for a123x, a123y, a123z being Element of BOOLEAN st a123x = s . [<*(GFA1AdderOutput ap,bm,cp),cin*>,and2a ] & a123y = s . [<*cin,dm*>,and2c ] & a123z = s . [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ] holds
(Following s) . (GFA2CarryOutput (GFA1AdderOutput ap,bm,cp),cin,dm) = 'not' ((a123x 'or' a123y) 'or' a123z)
set S = BitFTA1Str ap,bm,cp,dm,cin;
set C = BitFTA1Circ ap,bm,cp,dm,cin;
set A1 = GFA1AdderOutput ap,bm,cp;
set A2 = GFA2CarryOutput (GFA1AdderOutput ap,bm,cp),cin,dm;
set A1cin = [<*(GFA1AdderOutput ap,bm,cp),cin*>,and2a ];
set cindm = [<*cin,dm*>,and2c ];
set dmA1 = [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ];
let s be State of (BitFTA1Circ ap,bm,cp,dm,cin); :: thesis: for a123x, a123y, a123z being Element of BOOLEAN st a123x = s . [<*(GFA1AdderOutput ap,bm,cp),cin*>,and2a ] & a123y = s . [<*cin,dm*>,and2c ] & a123z = s . [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ] holds
(Following s) . (GFA2CarryOutput (GFA1AdderOutput ap,bm,cp),cin,dm) = 'not' ((a123x 'or' a123y) 'or' a123z)
let a123x, a123y, a123z be Element of BOOLEAN ; :: thesis: ( a123x = s . [<*(GFA1AdderOutput ap,bm,cp),cin*>,and2a ] & a123y = s . [<*cin,dm*>,and2c ] & a123z = s . [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ] implies (Following s) . (GFA2CarryOutput (GFA1AdderOutput ap,bm,cp),cin,dm) = 'not' ((a123x 'or' a123y) 'or' a123z) )
assume A1: ( a123x = s . [<*(GFA1AdderOutput ap,bm,cp),cin*>,and2a ] & a123y = s . [<*cin,dm*>,and2c ] & a123z = s . [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ] ) ; :: thesis: (Following s) . (GFA2CarryOutput (GFA1AdderOutput ap,bm,cp),cin,dm) = 'not' ((a123x 'or' a123y) 'or' a123z)
A2: ( [<*(GFA1AdderOutput ap,bm,cp),cin*>,and2a ] in the carrier of (BitFTA1Str ap,bm,cp,dm,cin) & [<*cin,dm*>,and2c ] in the carrier of (BitFTA1Str ap,bm,cp,dm,cin) & [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ] in the carrier of (BitFTA1Str ap,bm,cp,dm,cin) ) by ThFTA1S6;
A3: dom s = the carrier of (BitFTA1Str ap,bm,cp,dm,cin) by CIRCUIT1:4;
InnerVertices (BitFTA1Str ap,bm,cp,dm,cin) = the carrier' of (BitFTA1Str ap,bm,cp,dm,cin) by FACIRC_1:37;
then GFA2CarryOutput (GFA1AdderOutput ap,bm,cp),cin,dm in the carrier' of (BitFTA1Str ap,bm,cp,dm,cin) by ThFTA1S7;
hence (Following s) . (GFA2CarryOutput (GFA1AdderOutput ap,bm,cp),cin,dm) = nor3 . (s * <*[<*(GFA1AdderOutput ap,bm,cp),cin*>,and2a ],[<*cin,dm*>,and2c ],[<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ]*>) by FACIRC_1:35
.= nor3 . <*a123x,a123y,a123z*> by A1, A2, A3, FINSEQ_2:146
.= 'not' ((a123x 'or' a123y) 'or' a123z) by TWOSCOMP:def 28 ;
:: thesis: verum