let ap, bm, cp, dm be non pair set ; :: thesis: for cin being set st cin <> [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ] & not cin in InnerVertices (BitGFA1Str ap,bm,cp) holds
for s being State of (BitFTA1Circ ap,bm,cp,dm,cin)
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bm & a3 = s . cp & a4 = s . dm & a5 = s . cin holds
( (Following s,2) . (GFA1AdderOutput ap,bm,cp) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) & (Following s,2) . ap = a1 & (Following s,2) . bm = a2 & (Following s,2) . cp = a3 & (Following s,2) . dm = a4 & (Following s,2) . cin = a5 )
let cin be set ; :: thesis: ( cin <> [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ] & not cin in InnerVertices (BitGFA1Str ap,bm,cp) implies for s being State of (BitFTA1Circ ap,bm,cp,dm,cin)
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bm & a3 = s . cp & a4 = s . dm & a5 = s . cin holds
( (Following s,2) . (GFA1AdderOutput ap,bm,cp) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) & (Following s,2) . ap = a1 & (Following s,2) . bm = a2 & (Following s,2) . cp = a3 & (Following s,2) . dm = a4 & (Following s,2) . cin = a5 ) )
assume A1: ( cin <> [<*dm,(GFA1AdderOutput ap,bm,cp)*>,and2b ] & not cin in InnerVertices (BitGFA1Str ap,bm,cp) ) ; :: thesis: for s being State of (BitFTA1Circ ap,bm,cp,dm,cin)
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bm & a3 = s . cp & a4 = s . dm & a5 = s . cin holds
( (Following s,2) . (GFA1AdderOutput ap,bm,cp) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) & (Following s,2) . ap = a1 & (Following s,2) . bm = a2 & (Following s,2) . cp = a3 & (Following s,2) . dm = a4 & (Following s,2) . cin = a5 )
let s be State of (BitFTA1Circ ap,bm,cp,dm,cin); :: thesis: for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bm & a3 = s . cp & a4 = s . dm & a5 = s . cin holds
( (Following s,2) . (GFA1AdderOutput ap,bm,cp) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) & (Following s,2) . ap = a1 & (Following s,2) . bm = a2 & (Following s,2) . cp = a3 & (Following s,2) . dm = a4 & (Following s,2) . cin = a5 )
set S = BitFTA1Str ap,bm,cp,dm,cin;
set S1 = BitGFA1Str ap,bm,cp;
set C1 = BitGFA1Circ ap,bm,cp;
set A1 = GFA1AdderOutput ap,bm,cp;
set S2 = BitGFA2Str (GFA1AdderOutput ap,bm,cp),cin,dm;
set C2 = BitGFA2Circ (GFA1AdderOutput ap,bm,cp),cin,dm;
let a1, a2, a3, a4, a5 be Element of BOOLEAN ; :: thesis: ( a1 = s . ap & a2 = s . bm & a3 = s . cp & a4 = s . dm & a5 = s . cin implies ( (Following s,2) . (GFA1AdderOutput ap,bm,cp) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) & (Following s,2) . ap = a1 & (Following s,2) . bm = a2 & (Following s,2) . cp = a3 & (Following s,2) . dm = a4 & (Following s,2) . cin = a5 ) )
assume A2: ( a1 = s . ap & a2 = s . bm & a3 = s . cp & a4 = s . dm & a5 = s . cin ) ; :: thesis: ( (Following s,2) . (GFA1AdderOutput ap,bm,cp) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) & (Following s,2) . ap = a1 & (Following s,2) . bm = a2 & (Following s,2) . cp = a3 & (Following s,2) . dm = a4 & (Following s,2) . cin = a5 )
A3: ( ap in the carrier of (BitGFA1Str ap,bm,cp) & bm in the carrier of (BitGFA1Str ap,bm,cp) & cp in the carrier of (BitGFA1Str ap,bm,cp) ) by GFACIRC1:81;
reconsider s1 = s | the carrier of (BitGFA1Str ap,bm,cp) as State of (BitGFA1Circ ap,bm,cp) by FACIRC_1:26;
reconsider t = s as State of ((BitGFA1Circ ap,bm,cp) +* (BitGFA2Circ (GFA1AdderOutput ap,bm,cp),cin,dm)) ;
A4: GFA1AdderOutput ap,bm,cp in the carrier of (BitGFA1Str ap,bm,cp) by GFACIRC1:81;
A5: InputVertices (BitGFA1Str ap,bm,cp) misses InnerVertices (BitGFA2Str (GFA1AdderOutput ap,bm,cp),cin,dm) by LemmaX22;
dom s1 = the carrier of (BitGFA1Str ap,bm,cp) by CIRCUIT1:4;
then ( a1 = s1 . ap & a2 = s1 . bm & a3 = s1 . cp ) by A2, A3, FUNCT_1:70;
then ( (Following t,2) . (GFA1AdderOutput ap,bm,cp) = (Following s1,2) . (GFA1AdderOutput ap,bm,cp) & (Following s1,2) . (GFA1AdderOutput ap,bm,cp) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) ) by A4, A5, FACIRC_1:32, GFACIRC1:84;
hence (Following s,2) . (GFA1AdderOutput ap,bm,cp) = 'not' ((a1 'xor' ('not' a2)) 'xor' a3) ; :: thesis: ( (Following s,2) . ap = a1 & (Following s,2) . bm = a2 & (Following s,2) . cp = a3 & (Following s,2) . dm = a4 & (Following s,2) . cin = a5 )
A6: Following s,2 = Following (Following s) by FACIRC_1:15;
A7: ( ap in InputVertices (BitFTA1Str ap,bm,cp,dm,cin) & bm in InputVertices (BitFTA1Str ap,bm,cp,dm,cin) & cp in InputVertices (BitFTA1Str ap,bm,cp,dm,cin) & dm in InputVertices (BitFTA1Str ap,bm,cp,dm,cin) & cin in InputVertices (BitFTA1Str ap,bm,cp,dm,cin) ) by A1, ThFTA1S8;
then ( (Following s) . ap = a1 & (Following s) . bm = a2 & (Following s) . cp = a3 & (Following s) . dm = a4 & (Following s) . cin = a5 ) by A2, CIRCUIT2:def 5;
hence ( (Following s,2) . ap = a1 & (Following s,2) . bm = a2 & (Following s,2) . cp = a3 & (Following s,2) . dm = a4 & (Following s,2) . cin = a5 ) by A6, A7, CIRCUIT2:def 5; :: thesis: verum