let ap, bp, cp, dp be non pair set ; :: thesis: for cin being set
for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a123x, a123y, a123z being Element of BOOLEAN st a123x = s . [<*(GFA0AdderOutput ap,bp,cp),cin*>,and2 ] & a123y = s . [<*cin,dp*>,and2 ] & a123z = s . [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] holds
(Following s) . (GFA0CarryOutput (GFA0AdderOutput ap,bp,cp),cin,dp) = (a123x 'or' a123y) 'or' a123z
let cin be set ; :: thesis: for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a123x, a123y, a123z being Element of BOOLEAN st a123x = s . [<*(GFA0AdderOutput ap,bp,cp),cin*>,and2 ] & a123y = s . [<*cin,dp*>,and2 ] & a123z = s . [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] holds
(Following s) . (GFA0CarryOutput (GFA0AdderOutput ap,bp,cp),cin,dp) = (a123x 'or' a123y) 'or' a123z
set S = BitFTA0Str ap,bp,cp,dp,cin;
set C = BitFTA0Circ ap,bp,cp,dp,cin;
set A1 = GFA0AdderOutput ap,bp,cp;
set A2 = GFA0CarryOutput (GFA0AdderOutput ap,bp,cp),cin,dp;
set A1cin = [<*(GFA0AdderOutput ap,bp,cp),cin*>,and2 ];
set cindp = [<*cin,dp*>,and2 ];
set dpA1 = [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ];
let s be State of (BitFTA0Circ ap,bp,cp,dp,cin); :: thesis: for a123x, a123y, a123z being Element of BOOLEAN st a123x = s . [<*(GFA0AdderOutput ap,bp,cp),cin*>,and2 ] & a123y = s . [<*cin,dp*>,and2 ] & a123z = s . [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] holds
(Following s) . (GFA0CarryOutput (GFA0AdderOutput ap,bp,cp),cin,dp) = (a123x 'or' a123y) 'or' a123z
let a123x, a123y, a123z be Element of BOOLEAN ; :: thesis: ( a123x = s . [<*(GFA0AdderOutput ap,bp,cp),cin*>,and2 ] & a123y = s . [<*cin,dp*>,and2 ] & a123z = s . [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] implies (Following s) . (GFA0CarryOutput (GFA0AdderOutput ap,bp,cp),cin,dp) = (a123x 'or' a123y) 'or' a123z )
assume A1: ( a123x = s . [<*(GFA0AdderOutput ap,bp,cp),cin*>,and2 ] & a123y = s . [<*cin,dp*>,and2 ] & a123z = s . [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] ) ; :: thesis: (Following s) . (GFA0CarryOutput (GFA0AdderOutput ap,bp,cp),cin,dp) = (a123x 'or' a123y) 'or' a123z
A2: ( [<*(GFA0AdderOutput ap,bp,cp),cin*>,and2 ] in the carrier of (BitFTA0Str ap,bp,cp,dp,cin) & [<*cin,dp*>,and2 ] in the carrier of (BitFTA0Str ap,bp,cp,dp,cin) & [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] in the carrier of (BitFTA0Str ap,bp,cp,dp,cin) ) by ThFTA0S6;
A3: dom s = the carrier of (BitFTA0Str ap,bp,cp,dp,cin) by CIRCUIT1:4;
InnerVertices (BitFTA0Str ap,bp,cp,dp,cin) = the carrier' of (BitFTA0Str ap,bp,cp,dp,cin) by FACIRC_1:37;
then GFA0CarryOutput (GFA0AdderOutput ap,bp,cp),cin,dp in the carrier' of (BitFTA0Str ap,bp,cp,dp,cin) by ThFTA0S7;
hence (Following s) . (GFA0CarryOutput (GFA0AdderOutput ap,bp,cp),cin,dp) = or3 . (s * <*[<*(GFA0AdderOutput ap,bp,cp),cin*>,and2 ],[<*cin,dp*>,and2 ],[<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ]*>) by FACIRC_1:35
.= or3 . <*a123x,a123y,a123z*> by A1, A2, A3, FINSEQ_2:146
.= (a123x 'or' a123y) 'or' a123z by TWOSCOMP:def 24 ;
:: thesis: verum