let ap, bp, cp, dp be non pair set ; :: thesis: for cin being set
for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a123, a5 being Element of BOOLEAN st a123 = s . (GFA0AdderOutput ap,bp,cp) & a5 = s . cin holds
(Following s) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = a123 'xor' a5
let cin be set ; :: thesis: for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a123, a5 being Element of BOOLEAN st a123 = s . (GFA0AdderOutput ap,bp,cp) & a5 = s . cin holds
(Following s) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = a123 'xor' a5
set S = BitFTA0Str ap,bp,cp,dp,cin;
set C = BitFTA0Circ ap,bp,cp,dp,cin;
set A1 = GFA0AdderOutput ap,bp,cp;
set A1cin = [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ];
let s be State of (BitFTA0Circ ap,bp,cp,dp,cin); :: thesis: for a123, a5 being Element of BOOLEAN st a123 = s . (GFA0AdderOutput ap,bp,cp) & a5 = s . cin holds
(Following s) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = a123 'xor' a5
let a123, a5 be Element of BOOLEAN ; :: thesis: ( a123 = s . (GFA0AdderOutput ap,bp,cp) & a5 = s . cin implies (Following s) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = a123 'xor' a5 )
assume A1: ( a123 = s . (GFA0AdderOutput ap,bp,cp) & a5 = s . cin ) ; :: thesis: (Following s) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = a123 'xor' a5
A2: ( GFA0AdderOutput ap,bp,cp in the carrier of (BitFTA0Str ap,bp,cp,dp,cin) & cin in the carrier of (BitFTA0Str ap,bp,cp,dp,cin) ) by ThFTA0S6;
A3: dom s = the carrier of (BitFTA0Str ap,bp,cp,dp,cin) by CIRCUIT1:4;
InnerVertices (BitFTA0Str ap,bp,cp,dp,cin) = the carrier' of (BitFTA0Str ap,bp,cp,dp,cin) by FACIRC_1:37;
then [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] in the carrier' of (BitFTA0Str ap,bp,cp,dp,cin) by ThFTA0S7;
hence (Following s) . [<*(GFA0AdderOutput ap,bp,cp),cin*>,xor2 ] = xor2 . (s * <*(GFA0AdderOutput ap,bp,cp),cin*>) by FACIRC_1:35
.= xor2 . <*a123,a5*> by A1, A2, A3, FINSEQ_2:145
.= a123 'xor' a5 by TWOSCOMP:def 13 ;
:: thesis: verum