let ap, bp, cp, dp be non pair set ; :: thesis: for cin being set st cin <> [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] & not cin in InnerVertices (BitGFA0Str ap,bp,cp) holds
for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin holds
( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 )
let cin be set ; :: thesis: ( cin <> [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] & not cin in InnerVertices (BitGFA0Str ap,bp,cp) implies for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin holds
( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 ) )
assume A1: ( cin <> [<*dp,(GFA0AdderOutput ap,bp,cp)*>,and2 ] & not cin in InnerVertices (BitGFA0Str ap,bp,cp) ) ; :: thesis: for s being State of (BitFTA0Circ ap,bp,cp,dp,cin)
for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin holds
( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 )
let s be State of (BitFTA0Circ ap,bp,cp,dp,cin); :: thesis: for a1, a2, a3, a4, a5 being Element of BOOLEAN st a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin holds
( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 )
set S = BitFTA0Str ap,bp,cp,dp,cin;
set S1 = BitGFA0Str ap,bp,cp;
set C1 = BitGFA0Circ ap,bp,cp;
set A1 = GFA0AdderOutput ap,bp,cp;
set S2 = BitGFA0Str (GFA0AdderOutput ap,bp,cp),cin,dp;
set C2 = BitGFA0Circ (GFA0AdderOutput ap,bp,cp),cin,dp;
let a1, a2, a3, a4, a5 be Element of BOOLEAN ; :: thesis: ( a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin implies ( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 ) )
assume A2: ( a1 = s . ap & a2 = s . bp & a3 = s . cp & a4 = s . dp & a5 = s . cin ) ; :: thesis: ( (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 )
A3: ( ap in the carrier of (BitGFA0Str ap,bp,cp) & bp in the carrier of (BitGFA0Str ap,bp,cp) & cp in the carrier of (BitGFA0Str ap,bp,cp) ) by GFACIRC1:44;
reconsider s1 = s | the carrier of (BitGFA0Str ap,bp,cp) as State of (BitGFA0Circ ap,bp,cp) by FACIRC_1:26;
reconsider t = s as State of ((BitGFA0Circ ap,bp,cp) +* (BitGFA0Circ (GFA0AdderOutput ap,bp,cp),cin,dp)) ;
A4: GFA0AdderOutput ap,bp,cp in the carrier of (BitGFA0Str ap,bp,cp) by GFACIRC1:44;
A5: InputVertices (BitGFA0Str ap,bp,cp) misses InnerVertices (BitGFA0Str (GFA0AdderOutput ap,bp,cp),cin,dp) by LemmaX12;
dom s1 = the carrier of (BitGFA0Str ap,bp,cp) by CIRCUIT1:4;
then ( a1 = s1 . ap & a2 = s1 . bp & a3 = s1 . cp ) by A2, A3, FUNCT_1:70;
then ( (Following t,2) . (GFA0AdderOutput ap,bp,cp) = (Following s1,2) . (GFA0AdderOutput ap,bp,cp) & (Following s1,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 ) by A4, A5, FACIRC_1:32, GFACIRC1:47;
hence (Following s,2) . (GFA0AdderOutput ap,bp,cp) = (a1 'xor' a2) 'xor' a3 ; :: thesis: ( (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 )
A6: Following s,2 = Following (Following s) by FACIRC_1:15;
A7: ( ap in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) & bp in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) & cp in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) & dp in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) & cin in InputVertices (BitFTA0Str ap,bp,cp,dp,cin) ) by A1, ThFTA0S8;
then ( (Following s) . ap = a1 & (Following s) . bp = a2 & (Following s) . cp = a3 & (Following s) . dp = a4 & (Following s) . cin = a5 ) by A2, CIRCUIT2:def 5;
hence ( (Following s,2) . ap = a1 & (Following s,2) . bp = a2 & (Following s,2) . cp = a3 & (Following s,2) . dp = a4 & (Following s,2) . cin = a5 ) by A6, A7, CIRCUIT2:def 5; :: thesis: verum