let x, y, c be set ; :: thesis: ( x <> [<*y,c*>,'&' ] & y <> [<*c,x*>,'&' ] & c <> [<*x,y*>,'&' ] & c <> [<*x,y*>,'xor' ] implies for s being State of (BitAdderWithOverflowCirc x,y,c)
for a1, a2, a3 being Element of BOOLEAN st a1 = s . x & a2 = s . y & a3 = s . c holds
( (Following s,2) . (BitAdderOutput x,y,c) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . (MajorityOutput x,y,c) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) ) )
assume A1: ( x <> [<*y,c*>,'&' ] & y <> [<*c,x*>,'&' ] & c <> [<*x,y*>,'&' ] & c <> [<*x,y*>,'xor' ] ) ; :: thesis: for s being State of (BitAdderWithOverflowCirc x,y,c)
for a1, a2, a3 being Element of BOOLEAN st a1 = s . x & a2 = s . y & a3 = s . c holds
( (Following s,2) . (BitAdderOutput x,y,c) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . (MajorityOutput x,y,c) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) )
set f = 'xor' ;
set S1 = 2GatesCircStr x,y,c,'xor' ;
set S2 = MajorityStr x,y,c;
set A = BitAdderWithOverflowCirc x,y,c;
set A1 = BitAdderCirc x,y,c;
set A2 = MajorityCirc x,y,c;
let s be State of (BitAdderWithOverflowCirc x,y,c); :: thesis: for a1, a2, a3 being Element of BOOLEAN st a1 = s . x & a2 = s . y & a3 = s . c holds
( (Following s,2) . (BitAdderOutput x,y,c) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . (MajorityOutput x,y,c) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) )
let a1, a2, a3 be Element of BOOLEAN ; :: thesis: ( a1 = s . x & a2 = s . y & a3 = s . c implies ( (Following s,2) . (BitAdderOutput x,y,c) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . (MajorityOutput x,y,c) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) ) )
assume A2: ( a1 = s . x & a2 = s . y & a3 = s . c ) ; :: thesis: ( (Following s,2) . (BitAdderOutput x,y,c) = (a1 'xor' a2) 'xor' a3 & (Following s,2) . (MajorityOutput x,y,c) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) )
A3: ( x in the carrier of (2GatesCircStr x,y,c,'xor' ) & y in the carrier of (2GatesCircStr x,y,c,'xor' ) & c in the carrier of (2GatesCircStr x,y,c,'xor' ) ) by FACIRC_1:60;
A4: ( x in the carrier of (MajorityStr x,y,c) & y in the carrier of (MajorityStr x,y,c) & c in the carrier of (MajorityStr x,y,c) ) by FACIRC_1:72;
reconsider s1 = s | the carrier of (2GatesCircStr x,y,c,'xor' ) as State of (BitAdderCirc x,y,c) by FACIRC_1:26;
reconsider s2 = s | the carrier of (MajorityStr x,y,c) as State of (MajorityCirc x,y,c) by FACIRC_1:26;
reconsider t = s as State of ((BitAdderCirc x,y,c) +* (MajorityCirc x,y,c)) ;
InputVertices (2GatesCircStr x,y,c,'xor' ) = {x,y,c} by A1, FACIRC_1:57;
then A5: InputVertices (2GatesCircStr x,y,c,'xor' ) = InputVertices (MajorityStr x,y,c) by A1, Th21;
A6: ( InnerVertices (2GatesCircStr x,y,c,'xor' ) misses InputVertices (2GatesCircStr x,y,c,'xor' ) & InnerVertices (MajorityStr x,y,c) misses InputVertices (MajorityStr x,y,c) ) by XBOOLE_1:79;
dom s1 = the carrier of (2GatesCircStr x,y,c,'xor' ) by CIRCUIT1:4;
then ( a1 = s1 . x & a2 = s1 . y & a3 = s1 . c ) by A2, A3, FUNCT_1:70;
then ( (Following t,2) . (2GatesCircOutput x,y,c,'xor' ) = (Following s1,2) . (2GatesCircOutput x,y,c,'xor' ) & (Following s1,2) . (2GatesCircOutput x,y,c,'xor' ) = (a1 'xor' a2) 'xor' a3 ) by A1, A5, A6, FACIRC_1:32, FACIRC_1:64;
hence (Following s,2) . (BitAdderOutput x,y,c) = (a1 'xor' a2) 'xor' a3 ; :: thesis: (Following s,2) . (MajorityOutput x,y,c) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1)
dom s2 = the carrier of (MajorityStr x,y,c) by CIRCUIT1:4;
then ( a1 = s2 . x & a2 = s2 . y & a3 = s2 . c ) by A2, A4, FUNCT_1:70;
then ( (Following t,2) . (MajorityOutput x,y,c) = (Following s2,2) . (MajorityOutput x,y,c) & (Following s2,2) . (MajorityOutput x,y,c) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) ) by A1, A5, A6, Lm4, FACIRC_1:33;
hence (Following s,2) . (MajorityOutput x,y,c) = ((a1 '&' a2) 'or' (a2 '&' a3)) 'or' (a3 '&' a1) ; :: thesis: verum