defpred S1[ Element of NAT ] means for x, y being nonpair-yielding FinSeqLen of holds InputVertices ($1 -BitAdderStr x,y) = (rng x) \/ (rng y);
A1:
S1[ 0 ]
A3:
for i being Element of NAT st S1[i] holds
S1[i + 1]
proof
let i be
Element of
NAT ;
:: thesis: ( S1[i] implies S1[i + 1] )
assume A4:
S1[
i]
;
:: thesis: S1[i + 1]
let x,
y be
nonpair-yielding FinSeqLen of ;
:: thesis: InputVertices ((i + 1) -BitAdderStr x,y) = (rng x) \/ (rng y)
consider x' being
nonpair-yielding FinSeqLen of ,
z1 being non
pair set such that A5:
x = x' ^ <*z1*>
by Lm2;
consider y' being
nonpair-yielding FinSeqLen of ,
z2 being non
pair set such that A6:
y = y' ^ <*z2*>
by Lm2;
set S =
(i + 1) -BitAdderStr x,
y;
A7:
1
in Seg 1
by FINSEQ_1:3;
A8:
(
dom <*z1*> = Seg 1 &
<*z1*> . 1
= z1 )
by FINSEQ_1:def 8;
len x' = i
by FINSEQ_1:def 18;
then A9:
x . (i + 1) = z1
by A5, A7, A8, FINSEQ_1:def 7;
A10:
(
dom <*z2*> = Seg 1 &
<*z2*> . 1
= z2 )
by FINSEQ_1:def 8;
len y' = i
by FINSEQ_1:def 18;
then A11:
y . (i + 1) = z2
by A6, A7, A10, FINSEQ_1:def 7;
A12:
{z1,z2,(i -BitMajorityOutput x,y)} = {(i -BitMajorityOutput x,y),z1,z2}
by ENUMSET1:100;
A13:
rng x =
(rng x') \/ (rng <*z1*>)
by A5, FINSEQ_1:44
.=
(rng x') \/ {z1}
by FINSEQ_1:55
;
A14:
rng y =
(rng y') \/ (rng <*z2*>)
by A6, FINSEQ_1:44
.=
(rng y') \/ {z2}
by FINSEQ_1:55
;
A15:
(
z1 <> [<*z2,(i -BitMajorityOutput x,y)*>,'&' ] &
z2 <> [<*(i -BitMajorityOutput x,y),z1*>,'&' ] &
i -BitMajorityOutput x,
y <> [<*z1,z2*>,'&' ] &
i -BitMajorityOutput x,
y <> [<*z1,z2*>,'xor' ] )
by Th26;
(
x' = x' ^ {} &
y' = y' ^ {} )
by FINSEQ_1:47;
then
i -BitAdderStr x,
y = i -BitAdderStr x',
y'
by A5, A6, Th11;
hence InputVertices ((i + 1) -BitAdderStr x,y) =
(InputVertices (i -BitAdderStr x',y')) \/ ((InputVertices (BitAdderWithOverflowStr z1,z2,(i -BitMajorityOutput x,y))) \ {(i -BitMajorityOutput x,y)})
by A9, A11, Th27
.=
((rng x') \/ (rng y')) \/ ((InputVertices (BitAdderWithOverflowStr z1,z2,(i -BitMajorityOutput x,y))) \ {(i -BitMajorityOutput x,y)})
by A4
.=
((rng x') \/ (rng y')) \/ ({z1,z2,(i -BitMajorityOutput x,y)} \ {(i -BitMajorityOutput x,y)})
by A15, Th23
.=
((rng x') \/ (rng y')) \/ {z1,z2}
by A12, ENUMSET1:136
.=
((rng x') \/ (rng y')) \/ ({z1} \/ {z2})
by ENUMSET1:41
.=
(((rng x') \/ (rng y')) \/ {z1}) \/ {z2}
by XBOOLE_1:4
.=
(((rng x') \/ {z1}) \/ (rng y')) \/ {z2}
by XBOOLE_1:4
.=
(rng x) \/ (rng y)
by A13, A14, XBOOLE_1:4
;
:: thesis: verum
end;
thus
for i being Element of NAT holds S1[i]
from NAT_1:sch 1(A1, A3); :: thesis: verum