let S1, S2 be non empty non void unsplit gate`1=arity gate`2isBoolean ManySortedSign ; :: thesis: ( InnerVertices S1 misses InputVertices S2 implies for A1 being gate`2=den Boolean Circuit of S1
for A2 being gate`2=den Boolean Circuit of S2
for s being State of (A1 +* A2)
for s2 being State of A2 st s2 = s | the carrier of S2 holds
for n being Nat holds (Following s,n) | the carrier of S2 = Following s2,n )
assume A1:
InnerVertices S1 misses InputVertices S2
; :: thesis: for A1 being gate`2=den Boolean Circuit of S1
for A2 being gate`2=den Boolean Circuit of S2
for s being State of (A1 +* A2)
for s2 being State of A2 st s2 = s | the carrier of S2 holds
for n being Nat holds (Following s,n) | the carrier of S2 = Following s2,n
let A1 be gate`2=den Boolean Circuit of S1; :: thesis: for A2 being gate`2=den Boolean Circuit of S2
for s being State of (A1 +* A2)
for s2 being State of A2 st s2 = s | the carrier of S2 holds
for n being Nat holds (Following s,n) | the carrier of S2 = Following s2,n
let A2 be gate`2=den Boolean Circuit of S2; :: thesis: for s being State of (A1 +* A2)
for s2 being State of A2 st s2 = s | the carrier of S2 holds
for n being Nat holds (Following s,n) | the carrier of S2 = Following s2,n
let s be State of (A1 +* A2); :: thesis: for s2 being State of A2 st s2 = s | the carrier of S2 holds
for n being Nat holds (Following s,n) | the carrier of S2 = Following s2,n
let s2 be State of A2; :: thesis: ( s2 = s | the carrier of S2 implies for n being Nat holds (Following s,n) | the carrier of S2 = Following s2,n )
assume A2:
s2 = s | the carrier of S2
; :: thesis: for n being Nat holds (Following s,n) | the carrier of S2 = Following s2,n
defpred S1[ Nat] means (Following s,$1) | the carrier of S2 = Following s2,$1;
Following s,0 = s
by Th11;
then A3:
S1[ 0 ]
by A2, Th11;
A4:
for n being Nat st S1[n] holds
S1[n + 1]
thus
for n being Nat holds S1[n]
from NAT_1:sch 2(A3, A4); :: thesis: verum